Intel Corporation

Agere Systems Inc.

Anne Q Ye

Tony Lee Werner

Nitin N Garegrat

Michael Rotzin

Robert T Rhoades

Jeff DelChiaro

Ujwal Basavaraj Sajjanar

Richard Rauschmayer

Jonathan James Ashley

Kaichi Zhang

Keenan Terrell O'Brien

Sumeet Sanghvi

In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.

Multi-variate strided read operations for accessing matrix operands

A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.

Method and apparatus for generating filter tap weights and biases for signal dependent branch metric computation

Growing community of inventors

Sunnyvale, CA, United States of America

Anne Q Ye