Hewlett-packard Company

Anne P Scott

Jay E Fleischman

Jeffery C Brauch

Jeffrey C Brauch

An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

Memory address generator capable of row-major and column-major sweeps

An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

Apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces. Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. In one embodiment, a hierarchical one of the plural primary nodes includes plural secondary registers, each of the plural secondary registers individually selectable according to a secondary address presented on the serial data line. In another embodiment, a hierarchical one of the plural primary nodes includes plural secondary nodes, each of the plural secondary nodes individually selectable according to a secondary address presented on the serial data line. At least one of the plural secondary nodes includes plural tertiary registers, each of the plural tertiary registers individually selectable according to a tertiary address presented on the serial data line.

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Fort Collins, CO, United States of America

Anne P Scott