Texas Instruments Corporation

Anne Lombardot

Jean-Pierre Giacalone

Herve Catan

Francois Theodorou

Gilbert Laurenti

Douglas E Deao

Mark L Buser

Marc Couvrat

Shigeshi Abiko

Eric L Badi

Armelle Laine

Karim Djafarian

Vincent Gillet

Gael Clave

Jean-Marc Philippe Bachot

Yves Masse

Alain Boyadjian

Eric Ponsot

Jack Rosenzweig

Jean-Louis Tardieux

Walter A Jackson

Laurent Ichard

Emmanuel Ego

Frederic Nidegger

David Russell

N M Ganesh

An arithmetic unit, for example a multiply and accumulate (MAC) unitfor a processing engine includes a partial product reduction treeThe partial product reduction tree will generate carry results and provides a final output to a final adderconnected to the partial production reduction tree. Unbiased rounding logicis provided. A carry propagation tree is responsive to the carry results for anticipating a zero on each of N least significant bits of the final adder. When zero is anticipated on each of N least significant bits of the final adder, the carry propagation tree is operable to generate an output signalwhich is used by the unbiased rounding stage to force the (N+1)th least significant bit of the final adder to zero. Through the use of a carry propagation tree to predict, or anticipate zeros on the N least significant bits, unbiased rounding can be effected without a time penalty in that a carry propagation tree can be configured to be at least a rapid as the carry propagation of the final adder. Where a zero anticipation function is provided, this can also be mapped onto the carry propagation tree, thus providing an efficient hardware implementation through sharing of that hardware between functions.

Rounding mechanisms in processors

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A zero anticipation mechanism for an arithmetic unit of a processing engine includes an array of cells interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result prior to the arithmetic unit completing an arithmetic operation.

Zero anticipation method and apparatus

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Grasse, France

Anne Lombardot