Koninklijke Philips Corporation N.V.

Anne Lafage

Jean Gobert

Jacky Talayssat

Lien Nguyen-Phuc

A data processing arrangement comprises an input circuit [INP], an interconnection network [ICN] and a data processing circuit [PRC]. The input circuit [INP] forms successive groups of data [GRP] and, moreover, generates a basic control data item [BCD] and an additional control data item [SCD] for each group of data [GRP]. A basic control data item [BCD] indicates for each data item one of a plurality of terminals [] to which the data item should be applied. An additional control data item [SCD] indicates for each data item if this data item is valid [+] or not valid [&#x2212;]. The interconnection network [ICN] applies the successive groups of data to the terminals [] in dependence on the basic control data item [BCD] and on the additional control data item [SCD]. The interconnection network [ICN] applies a data item to the terminal indicated by the basic control data item [BCD] if the data item is valid [+]. If the data item is not valid [&#x2212;], the interconnection network [ICN] applies another valid data item instead. The data processing circuit [PRC] processes the data applied to the terminals [] in order to obtain an output data item. Such a data processing arrangement enables a low-cost processing of a set of data, some of which may be non-valid. The arrangement can be employed, for example, for filtering a set of pixels obtained from a MPEG4 decoder.

Processing of a data set

The present invention relates to a memory circuit (MEM) able to receive a first data block comprising a number of components and coming from an external memory (EXT) for them to be written (W) in an internal memory. The memory circuit is also able to supply (R) to an output device (FIL) a second data block comprising a component of said data. The memory circuit comprises data banks able to receive data words, and address controllers associated to the data banks and able to organize a reading or writing access of the data in the internal memory of the memory circuit, while minimizing the number of data banks used. Thus it is possible to rapidly read or write in the memory circuit at relatively low cost.

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Aix-en-Provence, France

Anne Lafage