Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Annamaria Rossi

Giona Fucili

Maurizio Nessi

Marcello Leone

Alberto Gola

Lorenzo Papillo

Andrea Pasquino

Rinaldo Castello

A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.

Successive approximation shift register with reduced latency

The synchronizing circuit of a digital drive system of an electric motor is configured to function in a closed loop or in an open loop mode by adding a minimum number of elements to the normal scheme of a closed loop synchronizing circuit. In practice, by adding only one programmable register and a pair of two-input de-multiplexers, the system is able to automatically switch from one mode of operation to the other mode. The programmable open loop mode permits compensating for the phase angle between the current flowing through the windings and the drive voltage applied thereto, as in case of a voltage mode driving.

Closed loop and open synchronization of the phase switchings in driving

A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.

Toggle flip-flop network with a reduced integration area

A digital-to-analog converter includes a potentiometric string suitable for realizing a relatively high number of bits that significantly reduces the silicon area requirement and simplifies mismatch compensation. The structure includes a first resistance string to realize a first DAC to convert a first number of most significative bits, and a second potentiometric string functionally connected in cascade to the first, but realized with MOS transistors. The structure of the invention allows the coupling of the two DACs in cascade by exploiting the MOS transistors that form the second potentiometric string, that is, the second DAC, thus avoiding the use of operational switches or amplifiers which may provide error sources. Moreover, the structure of the invention lends itself to the implementation of efficient compensation circuits for integral and differential linearity errors.

Compensated MOS string and DAC employing such a potentiometric string

A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).

Successive approximation and shift register without redundancy

A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

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Genoa, Italy

Annamaria Rossi