United Microelectronics Corp.

Anna Su

Water Lur

Neng H Shen

Jiun Y Wu

Jiunn Y Wu

A method for etching a conducting layer in a semiconductor device fabrication procedure is disclosed. The method provides for the formation of the conductor path with defined and precise control over the path width. The fabricated semiconductor device has a step-raised layer-covering structural configuration on a substrate, and the step-raised layer-covering structural configuration forms re-entrances when an insulation layer is formed over the step-raised layer-covering structure and the portion of the substrate surrounding the structure. The method includes forming a conducting layer on the insulation layer and then forming a shielding mask on the conducting layer for defining a conducting path with a predetermined pattern. The method further includes applying an anisotropic etching process for removing portions of the conducting layer not covered by the shielding mask. The method also forms residual stringers of the conducting layer in the re-entrances. The method then applies an anisotropic etching process to form first protecting layers covering the sidewalls of the conducting path, as well as second protecting layers covering the stringers, wherein the first protecting layers are thicker than the second protecting layers. The method finally applies an isotropic etching process to remove the second protecting layers and the stringers covered by the second protecting layers. Since the first protecting layers are thicker, the second protecting layers and their covered stringer can be removed completely before the first protecting layers are totally consumed.

Method for etching a conducting layer of the step-covered structure for

A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.

Planarized local oxidation by trench-around technology

A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon substrate that will form the device isolation region. A first trench is etched into the exposed portion of the substrate. A layer of silicon nitride is deposited over the insulating layer and within the trench. A layer of an aluminum-silicon alloy is deposited overlying the silicon nitride layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the silicon nitride layer. The nodules are oxidized to form silicon dioxide nodules. Using the silicon dioxide nodules as a mask, the silicon nitride layer is etched through to the insulating layer where it exists and to the silicon substrate surface where it is exposed and a set of narrow trenches is etched into the exposed portions of the substrate. The silicon substrate within the set of trenches is oxidized wherein the silicon is transformed to silicon dioxide and the silicon dioxide expands to fill the set of trenches. The silicon nitride layer and the silicon dioxide nodules within the opening are pushed up to align with the silicon nitride layer and the silicon dioxide nodules on either side of the opening. The remaining insulating layer and silicon nitride layer are removed wherein the silicon dioxide nodules are also removed completing the device isolation of the IC.

Technology for local oxidation of silicon

A method of local oxidation using trench-around technology is described. A first silicon oxide layer is deposited over the surface of a silicon substrate. A plurality of wide and narrow openings are etched through portions of the first silicon oxide layer not covered by a mask pattern to the silicon substrate. A layer of silicon nitride is patterned to form a set of spacers on the sidewalls of the patterned first silicon oxide layer which will fill the narrow openings. The first silicon oxide layer is partially etched away whereby the substrate within the central portions of the wide openings will be etched to form shallow trenches. The patterned first silicon oxide layer and the silicon nitride spacers are covered with spin-on-glass material which is baked and cured, then etched back leaving the spin-on-glass material only within the wide openings within the shallow trenches. The silicon nitride spacers are removed and deep trenches are etched into the silicon substrate under the spacers whereby the deep trenches are formed at the location of the narrow openings and at the outside edges of the wide openings flanking the shallow trenches. The deep trenches are filled with a second silicon oxide deposit. Field oxide regions are grown on within the shallow trenches, completing the device isolation.

A first insulating layer is deposited over the surface of a silicon substrate. Those portions of the first insulating layers not covered by a mask pattern are etched through to the silicon substrate so as to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A second insulating layer is deposited overlying the patterned first insulating layer. A layer of an aluminum-silicon alloy is deposited overlying the second insulating layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the second insulating layer. The second insulating layer is etched through to the first insulating layer where it exists and to the silicon substrate surface where the substrate is exposed within the wide and narrow openings. A first set of narrow trenches is etched into the exposed portions of the silicon substrate within the wide and narrow openings using the silicon nodules as a mask. A third insulating layer is deposited over the surface of the substrate and within the first set of trenches. The third insulating layer is etched back to leave spacers on the sidewalls of the first set of trenches which fill the trenches. A second set of trenches is etched into the silicon substrate not covered by a mask wherein the second set of trenches is immediately contiguous with the first set of trenches and wherein the first and second sets of trenches together correspond to the wide and narrow openings.

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Hsin-Chu, Taiwan

Anna Su