Cavium, Inc.

Anna Kujtkowski

Wilson Parkhurst Snyder, Ii

Albert Ma

Varada Ramesh Ogale

Thomas Frederick Hummel

Paul G Scrobohaci

In an embodiment, a method of providing quality of service (QoS) to at least one resource of a hardware processor includes providing, in a memory of the hardware processor, a context including at least one quality of service parameter and allocating access to the at least one resource of the hardware processor based on the quality of service parameter of the context, a device identifier, a virtual machine identifier, and the context.

Sharing resources in a multi-context computing system

In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

Approach for interfacing a pipeline with two or more interfaces in a processor

A method and a system embodying the method for a memory address alignment, comprising configuring one or more naturally aligned buffer structure(s); providing a return address pointer in a buffer of one of the one or more naturally aligned buffer structure(s); determining a configuration of the one of the one or more naturally aligned buffer structure(s); applying a modulo arithmetic to the return address and at least one parameter of the determined configuration; and providing a stacked address pointer determined in accordance with the applied modulo arithmetic, is disclosed.

Method and an apparatus for memory address allignment

An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.

Method and system for compressing data for a translation look aside buffer (TLB)

In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.

Distributing resource requests in a computing system

A method and a system embodying the method for virtualization of a quality of service, comprising associating a packet received at an interface with an aura via an aura identifier; determining configuration parameters for the aura; determining a pool for the aura; determining the state of the pool resources, the resources comprising a level of buffers available in the pool and a level of buffers allocated to the aura; and determining a quality of service for the packet in accordance with the determined state of the pool and the configuration parameters for the aura, is disclosed.

Growing community of inventors

Rochdale, MA, United States of America

Anna Kujtkowski