Google Inc.

Anna Darling Goldie

Azalia Mirhoseini

Jeffrey Adgate Dean

Chian-Min Richard Ho

Mustafa Nazim Yazgan

Quoc V Le

James Laudon

Shen Wang

Wenjie Jiang

Young-Joon Lee

Emre Tuncer

Roger David Carpenter

Ebrahim Songhori

Ya Wang

Anand Babu

William Hang

Omkar Pathak

Kavya Srinivasa Setty

Benoit Steiner

Hieu Hy Pham

Sudip Roy

Hanxiao Liu

Qiumin Xu

Daniel Lin-Kit Wong

Amirali Abdolrashidi

Yanqi Zhou

Chao Ma

Phitchaya Mangpo Phothilimthana

Aspects of the disclosure are directed to automatically determining floor planning in chips, which factors in memory macro alignment. A deep reinforcement learning (RL) agent can be trained to determine optimal placements for the memory macros, where memory macro alignment can be included as a regularization cost to be added to the placement objective as a RL reward. Tradeoffs between the placement objective and alignment of macros can be controlled by a tunable alignment parameter.

Alignment cost for integrated circuit placement

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for compiler optimizations using a compiler optimization network. One of the methods includes receiving an input program, wherein the input program defines a graph of operation modules, wherein each node in the graph is a respective operation module, and each edge between nodes in the graph represents one operation module receiving the output generated by another operation module. The input program is processed by a compiler optimization network comprising a graph-embedding network that is configured to encode operation features and operation dependencies of the operation modules of the input program into a graph embedding representation and a policy network that is configured to generate an optimization action for each of one or more nodes encoded in the graph embedding representation. The compiler optimization network generates an output optimization plan comprising one or more optimization actions for the input program.

Learned graph optimizations for compilers

Example aspects of the present disclosure are directed to systems and methods for generation of improved language embeddings (e.g., entity embeddings for natural language tokens) which provide improved model performance. In addition, the proposed techniques require less computational consumption relative to previous approaches.

Systems and methods for generating improved embeddings while consuming fewer computational resources

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Generating integrated circuit placements using neural networks

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Generating integrated circuit floorplans using neural networks

A method for determining a placement for machine learning model operations across multiple hardware devices includes receiving data specifying machine learning operations, and determining a placement that assigns each of the operations specified by the data to a respective device from the multiple hardware devices. Determining the placement includes: generating, from the data, a respective operation embedding for each of the operations; grouping the operations into multiple operation groups, comprising processing each of the respective operation embeddings using a grouper neural network having multiple grouper parameters, in which the grouper neural network is configured to, for each of the operations, process the operation embedding for the operation in accordance with first values of the grouper parameters to generate a grouper output that assigns the operation to an operation group from the multiple operation groups; and assigning each of the operation groups to a respective device from the multiple hardware devices.

Hierarchical device placement with reinforcement learning

Growing community of inventors

Mountain View, CA, United States of America

Anna Darling Goldie