Stmicroelectronics S.a.

Mentor Graphics Corporation

Anna Asquini

Vincent Vallet

A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

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Corenc, France

Anna Asquini