Taiwan Semiconductor Manufacturing Comp. Ltd.

Ann Luh

Kuo-Chin Chang

Clinton Chao

Tjandra Winata Karta

Jerry Tzou

Szu Wei Lu

Szu-Wei Lu

Yung-Liang Kuo

Hsu Ming Cheng

Shu-Min Chen

Andy Hong

Oliver Wu

Frank Hwang

Wen-Hung Wu

Pi-Huang Lee

Kathy Wang

A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 &#x3bc;m. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Silicon-based thin substrate and packaging schemes

A universal system for testing different semiconductor devices provides a probe head with a probe pattern that may be used to test different test patterns formed on different semiconductor devices. Each of a plurality of bumps or pads of the test pattern contacts a corresponding probe of the probe head to enable the semiconductor device to be tested. The universal probe head may additionally or alternatively include a substrate design on the probe head that provides a pattern on the substrate of the probe head that may be used in conjunction with different patterns formed on a plurality of different printed circuit boards for testing different semiconductor devices.

Universal array type probe card design for semiconductor device testing

A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 &#x3bc;m. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 &#x3bc;m. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

A computer integrated manufacturing system executes a program process that performs a capacity planning method that allocates usage of a plurality of manufacturing elements of a manufacturing enterprise by major and minor apparatus, squeezing for overhead cost consideration, and site balance for maintain basic operation. The program process begins by receiving at least one fabrication forecast describing scheduling and types of product lots that are predicted to be fabricated within a first period of time by the manufacturing enterprise from at least one order management system of the manufacturing enterprise. Rolling statistics of products lots fabricated during a second period of time are retrieved from a data retention device of the computer integrated manufacturing system. Capacity planning for the allocation of the product lot predicted to be fabricated by the manufacturing elements is performed.

Heuristics for efficient supply chain planning in a heterogeneous production line

Growing community of inventors

Hsin-Chu, Taiwan

Ann Luh