Force10 Networks, Inc.

Infinera Corporation

Ann Gui

Glenn C Poole

Joanna Lin

Heeloo Chung

Brad Danofsky

David Haddad

Krishnamurthy Subramanian

Biao Lu

Rajan Rao

Ping Pan

Joel R Goergen

Jan Bialkowski

Khuzema Pithewan

Sri Mohana Satya Srinivas Singamsetty

Anthony Jorgenson

Maneesh Jain

Andy Liu

Eugene W Lee

Somsubhra Sikdar

An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.

Packet segmentation with different segment sizes for a switch fabric

A network packet is segmented for transfer through a switch fabric. The last segment of the packet is allowed to exceed the maximum size of previous segments so as to increase the switch fabric utilization. Other features are also provided.

Segmentation of network packets for a switch fabric

A method for detecting the liveliness and synchronizing the control-plane and data-plane on protecting connections in a shared mesh network environment through methods for probing the protecting connection conditions by sending in-band messages; and synchronization of control plane and data plane by using LSP-ping messages on the protecting connections.

Supporting OAM on protecting connections in shared mesh protection environment

FIFO buffer with multiple stream packet segmentation

A method comprising the steps of receiving a signal indicative of a failure of a working connection in a mesh network having a headend node, a tailend node and an intermediate node, and having a protecting connection, and transmitting an activation message via the protecting connection from at least one of the headend node and the tailend node to the intermediate node for activating the protecting connection.

Activation signaling in transport networks

A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Dual signaling format switch fabric with multiplex capability

In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Several lanes are coded separately in this manner, and then multiplexed on a common channel. Alignment sequences in the control character sequences, as well as scrambler seeds, are set to avoid synchronization of patterns generated among all lanes, which would tend to confuse a receiving serdes and/or phase-locked loop that recovers timing from the multiplexed scrambled signals.

Multiplexed multilane hybrid scrambled transmission coding

Multiple comparators compare the enable and priority values for multiple inputs and select a winner from one of the inputs. Multiple comparator stages each include one or more of the comparators. Each comparator stage selects winners from the outputs of a preceding comparator stage. The overall winners are those inputs that are winners in each comparator stage. If there are multiple overall winners, a second arbitration is preformed to identify an ultimate winner.

Multistage cascade arbiter

A data rate controller controls a rate that data is transferred over a backplane in a network processing device. A bandwidth allocator allocates bandwidth to an input port for transmitting data over the backplane to an output port. A bandwidth limiter identifies a maximum allowable bandwidth the input port is allocated on the backplane. A bandwidth tracker identifies an amount of bandwidth currently allocated to the input port for transmitting data over the backplane to the output port. When the current allocated bandwidth is used up, the data rate controller prevents that input port from connecting to output ports through the backplane until more bandwidth is allocated.

Growing community of inventors

Cupertino, CA, United States of America

Ann Gui