International Business Machines Corporation

Ann E Huffman

Stamatis Vassiliadis

Michael Putrino

Gerald George Pechanek

Brice J Feal

Agnes Yee Ngai

The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

Apparatus and method for prediction of zero arithmetic/logic results

Method and apparatus for modified carry-save determination of

An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B)&gt;0, or a second branch condition ((Q+R)-B).ltoreq.0.

Apparatus for branch prediction for computer instructions

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Johnson City, NY, United States of America

Ann E Huffman