International Business Machines Corporation

Ann Chen Wu

James David Strom

Grant Paul Kesselring

Scott Trcka

John Michael Borkenhagen

Andrew Douglas Davies

Erik S Unterborn

Rashmi Bindu

Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.

Dual loop charge pump for enhanced reliability and power consumption

Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

High frequency AC coupled self-biased divider

A phase locked loop having a charge pump is described. The charge pump relies on close matching of FETs (Field Effect Transistor) electrical parameters to FETs in a current reference circuit. To achieve close matching of FET electrical performance, FEOL (Front End Of Line), comprising all FET shapes, of the current pump is identical in shapes and layout to the current reference circuit. BEOL (Back End Of Line) differs between the charge pump and the current reference circuit. The charge pump and the current reference circuit are arranged in a row. A shield circuit having FEOL shapes and layout identical to the current pump may be placed at each end of the row.

Higher yielding improved matching reference circuit especially applicable for high speed mixed signal applications and phase locked loops and charge pumps

An embodiment of the invention may include a method and structure for determining a failure in a guard ring of a chip. The method may include measuring a current frequency of oscillation of a crack check circuit located within a guard ring. The method may include comparing the frequency to a baseline frequency of oscillation of the crack check circuit. The current frequency and baseline frequency may be normalized using a set of bypass lines. The method may include determining there is a failure of the guard ring based on the difference between the normalized frequency of oscillation and the baseline normalized frequency of oscillation.

Guard ring monitor

A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Integrated circuit voltage-controlled oscillator with late-stage fabrication tuning

A differential charge pump circuit for use in a phase-locked loop (PLL) circuit is disclosed. The circuit includes a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The circuit controls a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node.

Efficient differential charge pump with sense and common mode control

A system and apparatus relating to a differential charge pump circuit for use in a phase-locked loop (PLL) circuit. A differential charge pump circuit can include a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The nodes are inputs to one of the sense amplifiers. The differential charge pump circuit is configured to control a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node. The differential charge pump circuit can also include a transistor with a gate coupled to an output of a sense amplifier. The voltage at the first node can be controlled by the sense amplifier and the transistor.

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Hopewell Junction, NY, United States of America

Ann Chen Wu