Intel Corporation

Sony Corporation

Sony Group Corporation

Ankush Varma

Krishnakanth Venkata Sistla

Vivek Garg

Ian M Steiner

Avinash N Ananthakrishnan

Martin Rowland

Efraim Rotem

Nikhil Gupta

Alexander Gendler

Jeremy J Shrall

Vasudevan Srinivasan

Eliezer Weissmann

Stephen H Gunther

Nir Rosenzweig

Eric J DeHaemer

Matthew M Bace

Eugene Gorbatov

Guy M Therien

Chris Poirier

Andrew D Henroid

Adwait Purandare

John Joseph Browne

Yen-Cheng Liu

Robert E Gough

Chris MacNamara

Jeffrey D Chamberlain

Tejpal Singh

Ripan Das

Jason W Brandt

Alon Naveh

Dheeraj R Subbareddy

David W Browning

Gerald S Pasdast

George Zacharias Chrysos

Vedaraman Geetha

Ashish V Choubal

Anil Aggarwal

Nagasubramanian Gurumoorthy

Mahesh K Kumashikar

Venkatesh Ramamurthy

William R Halleck

Guy G Sotomayor

Corey D Gough

Nevine Nassif

William Johnson Bowhill

Barnes Cooper

Devadatta V Bodas

Hang T Nguyen

James G Hermerding, Ii

Tod F Schiff

Neil W Songer

Jonathan M Eastep

James Steven Burns

Brian J Griffith

Nazar Syed Haider

Xiuting C Man

Robert G Blankenship

Nadav Shulman

Inder M Sodhi

Kristoffer Fleming

Mark P Seconi

Federico Ardanaz

Daniel J Ragland

Anupama Suryanarayanan

Daniel G Borkowski

Ariel Szapiro

Arik Gihon

David Hunt

Yogesh Bansal

Buck Gremel

Mark Rowland

Jianwei Dai

Doron Rajwan

Andrew J Herdrich

Russell Jerome Fenger

Tessil Thomas

Dean A Mulla

Viktor D Vogman

Swadesh Choudhary

Jonathan P Douglas

Srihari Makineni

Sandeep Ahuja

Tomasz Kantecki

Malini Krishnan Bhandaru

James R Vash

Alexander Lyakhov

Adrian C Moga

Dorit Shapira

Edward R Stanford

Shrikant M Shah

Scott P Bobholz

Vasudev Bibikar

Lakshmipriya Seshan

Esfir Natanzon

Robin A Steinbrecher

Christopher Allan Poirier

Monica C Wong-Chan

Narayanan Natarajan

Susan F Smith

Srikrishnan Venkataraman

In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

Register interface for computer processor

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Current control for a multicore processor

A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

Performance level control in a data processing apparatus

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

Hardware-assisted core frequency and voltage scaling in a poll mode idle loop

An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

Apparatus and method to detect power supply security attack and risk mitigation

A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.

Real-time power meter for optimizing processor power management

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Multiple dies hardware processors and methods

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Apparatus and method for dynamic control of microprocessor configuration

In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

System, apparatus and method for globally aware reactive local power control in a processor

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Hillsboro, OR, United States of America

Ankush Varma