Intel Corporation

Ankur N Shah

Joydeep Ray

Abhishek R Appu

Altug Koker

Travis T Schluessler

Murali Ramadoss

Elmoustapha Ould-Ahmed-Vall

Balaji Vembu

Prasoonkumar Surti

David M Puffer

Deepak Shashidhar Vembar

Jonathan Kennedy

Hugues Labbe

Kai Xiao

Michael Apodaca

Atsuo Kuwahara

Aditya Navale

Chandrasekaran Sakthivel

Radhakrishnan Venkataraman

Jeffery S Boles

Brent E Insko

Vasanth Ranganathan

Kamal Sinha

Subramaniam M Maiyuran

Nikos Kaburlasos

Adam T Lake

Jacek Kwiatkowski

Niranjan L Cooray

Kiran Chand Veernapu

Tomer Bar-On

Pattabhiraman K

Wenyin Fu

Bhushan M Borole

Bryan R White

Ben J Ashbaugh

Gabor Liktor

Aravindh V Anantaraman

James M Holland

Hema Chand Nalluri

James A Valerio

John G Gierach

David J Cowperthwaite

Sameer Kp

Varghese George

Rajesh M Sankaran

Kun Tian

Peter L Doyle

Lakshminarayanan Striramassarma

Mike MacPherson

Valentin Andrei

David M Cimini

Sayan Lahiri

Johannes Guenther

Nicolas C Galoppo Von Borries

Josh B Mastronarde

Philip R Laws

Eric J Hoekstra

Jefferson Amstutz

Linda L Hurd

Mahesh S Natu

Devan Burke

Vivek Garg

Rajeev K Nalawadi

Saurabh Sharma

Guei-Yuan Lueh

Karthik Vaidyanathan

Scott R Janus

John H Feit

Ingo Wald

Abhishek Venkatesh

Lakshminarayana Pappu

Supratim Pal

Andrew T Lauritzen

Arthur Hunter, Jr

Jianfang Olena Zhu

Carson Brownlee

Bo Qiu

Vivek Tiwari

Wei Zhang

Siddhartha Chhabra

Sanjeev S Jahagirdar

Justin E Gottschlich

Paul S Diefenbaugh

Anbang Yao

John Charles Weast

Eriko Nurvitadhi

Sara S Baghsorkhi

Xiaoming Chen

Jason Daniel Tanner

Changliang Wang

Nadathur Rajagopalan Satish

Selvakumar Panneer

Utkarsh Y Kakaiya

Liwei Ma

Daniel Nemiroff

Farshad Akhbari

Wei-Yu Chen

Kevin Nealis

Arthur Jeremy Runyan

Jeremy Bottleson

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

Local memory translation table accessed and dirty flags

An infrastructure for a platform immersive experience is described. An example of an apparatus includes a microcontroller to receive control parameters for platform lighting options for a computing system and information regarding current system conditions for the computing system, and generate control instructions for a lighting pattern for a set of lights based at least in part on the control parameters and the information regarding current system conditions; and host control circuitry to receive the control instructions for the lighting pattern from the microcontroller, and provide control signals to control the set of lights.

Infrastructure for platform immersive experience

Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.

Interconnect fabric link width reduction to reduce instantaneous power consumption

In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

Dynamic voltage and frequency scaling for discrete graphics systems

Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load/store pipeline. The processing resource is operable to receive a memory access message including a pointer and a memory type identifier indicative of the pointer representing a generic pointer. The processing resource is further operable to output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type. The load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.

Providing native support for generic pointers in a graphics processing unit

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

Graphics system with additional context

Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

Graphics processor data access and sharing

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Scalable I/O virtualization interrupt and scheduling

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Multi-tile memory management

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Graphics anti-aliasing resolve with stencil mask

Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Apparatus and method for a virtualized display

Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

Growing community of inventors

Folsom, CA, United States of America

Ankur N Shah