Memc Electronic Materials, Inc.

Ankur H Desai

Michael S Wisnieski

Robert Wendell Standley

David I Golland

David Louis Vadnais

Harold E Hall, Jr

Troy W Adcock

Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 .mu.ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, T.sub.t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T.sub.t.

Flattening process for epitaxial semiconductor wafers

Apparatus for determining the flatness of a generally circular polishing pad through direct measurement of the pad for use in maintaining the flatness of the pad and the flatness of surfaces of articles polished on the polishing pad of a polisher. The apparatus includes a measuring device, a frame mounting the measuring device being capable of measuring a distance between an upper surface of the polishing pad and a reference plane at plural locations along the polishing pad. The apparatus further includes a controller for controlling the measuring device. The controller is configured to indicate whether the flatness of the pad falls outside a predetermined specification.

Method and apparatus for controlling flatness of polished semiconductor

A semiconductor wafer polisher of the present invention for polishing at least one semiconductor wafer to flatten a first face of the wafer and reduce the thickness of the wafer from an initial thickness t.sub.1 to a predetermined final thickness t.sub.2. The polisher comprises a first surface including a polishing surface portion, a second surface including a second surface portion, and a wafer carrier for holding the semiconductor wafer between the polishing surface portion and the second surface portion. At least one polishing limiter is between the first and second surfaces for limiting the reduction in thickness of the wafer. The wafer carrier and polishing limiter are integrally formed such that the polishing limiter and wafer carrier constitute a single unitary piece. The polishing limiter has at least one rubbing surface adapted for rubbing against one of the first and second surfaces and is sized and configured such that the rubbing surface is spaced axially from the one of the first and second surfaces when the semiconductor wafer has the thickness t.sub.1 and such that the rubbing surface rubs against the one of the first and second surfaces and the polishing limiter extends from the second surface to the first surface when the semiconductor wafer has the thickness t.sub.2. The polishing limiter has a greater resistance to polishing than that of the semiconductor wafer such that the polishing limiter prevents the polishing surface and the second surface portion from further moving axially toward each other when the polishing limiter extends from the second surface to the first surface to prevent the wafer from being reduced in thickness beyond the thickness t.sub.2.

Growing community of inventors

St. Peters, MO, United States of America

Ankur H Desai