Ansys, Inc.

Samsung Electronics Co., Ltd.

Ankur Gupta

Pranav K Mistry

Sajid Hassan Sadi

Abhijit Z Bendale

Joao Moreno Geada

Nicholas Lee Rethman

Fannie Fontanel

Michael Sapienza

Ondrej Texler

Hyun Jae Kang

Anthony Sylvain Jean-Yves Liot

Dimitar Petkov Dinev

Siddarth Ravichandran

Nick Rethman

Image generation using a hierarchical, model-based system includes generating a first region of an image using a first neural network model. The first region of the image is provided to a second neural network model as input. A second region of the image is generated using the second neural network model. The second region of the image shares a boundary with at least a portion of the first region of the image.

Hierarchical model-based generation of images

Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

Systems and methods for accurate voltage impact on integrated timing simulation

Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit design is received, the integrated circuit design including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit design based on a vulnerability metric of the vulnerable cell. A power analysis of a portion of the integrated circuit design is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.

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San Jose, CA, United States of America

Ankur Gupta