Samsung Electronics Co., Ltd.

International Business Machines Corporation

Google Inc.

Cadence Design Systems, Inc.

Texas Instruments Corporation

Emc IP Holding Company LLC

Informatica Corporation

Ankur Gupta

Abhijit Z Bendale

Michael Sapienza

Parvinder Kumar Rana

Lava Kumar Pulluru

Fannie Fontanel

Smita Hashim

Xiaoqiao Meng

Amin Charaniya

Timothy P Ellison

Aileen Tang

Sreedhar B Kodali

James Dowdell

Neil G M Richards

Sivasakthi Thirugnanapandi

Vivek Chickermane

Manish Pandey

Patrick Gallagher

Pinhong Chen

Sandeep Bhatia

Qi Wang

Huan-Chih Tsai

Christina Chu

Steven Sharp

Pranav K Mistry

Krzysztof Duleba

Manish Chandra Joshi

Yonghao Chen

Prabhu Balasubramanian

Shu Niu

Jamie Samdal

Graham Jenkin

Jessica Mignone

Audrey Yang

Doris Bruneder

Shunguo Yan

Rajat Chauhan

Ramakanth Kanagovi

Luuk Van Dijk

Richard Grondin

Hitesh Mohan Kumar

Mitchell W Hines

Mukul Agarwal

Sagar Kumar

Tobing Soebroto

Richard M Chou

Vikas Narang

Abhishek Kesarwani

Vinayak Borkar

Bhupendra Chopra

Rahul R Belekar

Hendy Kosasih

Yonghoa Chen

Aurosikha

Himanshu Saxena

Anjana P Pai

Venkata Surya Narayana Raju Datla

Premkumar Sj

Manikam Muthiah

Shuvadeep Kumar

Described embodiments provide systems and methods for identifying malicious attempts to detect vulnerabilities in an application. At least one processor may determine a mean and a standard variation of character counts of each of a plurality of characters from a plurality of sets of data. The at least one processor may determine a distance metric for each of the characters in each of the sets of data. For a corresponding set of data, the at least one processor may determine a number of outliers to determine whether the corresponding set of data is anomalous.

System and method for detecting malicious attempts to discover vulnerabilities in a web application

Embodiments herein disclose an OTP low power circuit and methods for providing bias voltages using a single regulator. The circuit includes a Bitcell, a diode drop, a charge pump, a combinational logic controller, a program current sink load, and a read current sink load. The Bitcell includes programmable word lines and read lines, and is configured to operate in either a programmable mode or a read mode. The diode drop is configured to provide a second bias voltage to drive the read lines and the single regulator is configured to provide a first bias voltage to drive the WP in the read mode. The charge pump is configured to provide a third bias voltage to drive the WP in the program mode.

One time programmable (OTP) low power circuits and methods for providing bias voltages to wordlines

The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Circuits for power down leakage reduction in random-access memory

A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.

Bitline precharge system for a semiconductor memory device

A system and method for a master platform includes receiving first pose data associated with an image sensor of a first device, and a first semantic map generated by the first device, the first semantic map including a simplified object representation in a coordinate space of the first device. The master platform also receives second pose data associated with an image sensor of a second device, and a second semantic map generated by the second device, the second semantic map including a simplified object representation in a coordinate space of the second device. A shared simplified object representation common to the first and semantic maps is identified. The master platform further combines the first semantic and second semantic maps based on the first and second pose data. The first pose data, first semantic map, second pose data, and second semantic map are associated with a common time interval.

Semantic mapping for low-power augmented reality using dynamic vision sensor

An untethered apparatus for performing inside-out device tracking based on visual-inertial simultaneous location and mapping (SLAM) includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, an inertial measurement unit (IMU) sensor configured to collect IMU data associated with motion of the apparatus at a predetermined interval, a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to accumulate DVS sensor output over a sliding time window, the sliding time window including the predetermined interval, apply a motion correction to the accumulated DVS sensor output, the motion correction based on the IMU data collected over the predetermined interval, generate an event-frame histogram of DVS sensor events based on the motion correction, and provide the event-frame histogram of the DVS sensor events and the IMU data to a visual inertial SLAM pipeline.

CMOS-assisted inside-out dynamic vision sensor tracking for low power mobile platforms

In an approach for managing network sockets, a computer receives a request to create a network socket to transfer data. The computer identifies information associated with the received request, including one or more of: a default network protocol, one or more supported network protocols, ahead of time initialization, a data transfer policy, a failure policy, and a security policy. The computer creates a second level hash map based on the identified information, wherein the second level hash map includes the supported network socket protocols and a connection state. The computer determines a network protocol to utilize associated with the received request. The computer establishes a connection for the network socket over the determined network protocol.

Managing network sockets

An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Level shifter circuits

A method for managing error messages includes obtaining, by a message resolution manager, a plurality of error messages, performing an error message consecutive deduplication on the plurality of error messages to obtain a plurality of deduplicated error messages, generating a plurality of message sequences using the plurality deduplicated error messages, applying a message sequence frequency algorithm to the plurality of message sequences to obtain a high severity message sequence list, and initiating an error message resolution on at least one message sequence specified in the high severity message sequence list.

System and method for resolving error messages in an error message repository

An apparatus includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, and a complementary metal-oxide-semiconductor (CMOS) image sensor configured to output frames of image data. The apparatus further includes a hybrid feature handler configured to receive, as an input, one or more of a DVS output or a CMOS image sensor output, and provide tracked features to a visual-inertial simultaneous location and mapping (SLAM) pipeline performing inside-out device tracking, and a sensor scheduler configured to switch off the CMOS image sensor based on a current value of one or more CMOS control factors.

A method for semi-dense depth estimation includes receiving, at an electronic device, a control signal of a speckle pattern projector (SPP and receiving from each sensor of a dynamic vision sensor (DVS) stereo pair, an event stream of pixel intensity change data, wherein the event stream is time-synchronized with the control signal of the SPP. The method further includes performing projected light filtering on the event stream of pixel intensity change data for each sensor of the DVS stereo pair, to generate synthesized event image data, the synthesized event image data having one or more channels, each channel based on an isolated portion of the event stream of pixel intensity change data and performing stereo matching on at least one channel of the synthesized event image data for each sensor of the DVS stereo pair to generate a depth map for at least a portion of the field of view.

Semi-dense depth estimation from a dynamic vision sensor (DVS) stereo pair and a pulsed speckle pattern projector

A system for determining and tracking camera pose includes a dynamic vision sensor (DVS) configured to generate a current DVS image, an inertial measurement unit (IMU) configured to generate inertial data, and a memory. The memory is configured to store a 3-dimensional (3D) map of a known 3D environment. The system may also include a processor coupled to the memory. The processor is configured to initiate operations including determining a current camera pose for the DVS based on the current DVS image, the inertial data, the 3D map, and a prior camera pose.

Camera pose determination and tracking

An apparatus includes a dynamic vision sensor (DVS) configured to output an asynchronous stream of sensor event data, a CMOS image sensor configured to output frames of image data, an inertial measurement unit (IMU), a processor and a memory. The memory contains instructions, which when executed by the processor, cause the apparatus to generate a semantic segmentation of a time-stamped frame, which is based on one or more of an output of the CMOS image sensor, or a synthesized event frame based on an output from the DVS and an output from the IMU over a time interval. The semantic segmentation includes a semantic label associated with a region of the time-stamped frame. When executed, the instructions further cause the apparatus to determine, based on the semantic segmentation, a simplified object representation in a coordinate space, and update a stable semantic map based on the simplified object representation.

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Bengaluru, India

Ankur Gupta