Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Elpida Memory, Inc.

Stmicroelectronics Pvt. Ltd.

Ankur Goel

Setti Shanmukheswara Rao

Dharmendra Kumar Rai

Donald Albert Evans

Richard John Stephani

Rasoju Veerabadra Chary

Manish Trivedi

Shetti Shanmukheshwara Rao

Shishir Kumar

Dennis E Dudeck

Ronald James Wozniak

Gordon W Priebe

Mudit Bhargava

Krishman S Rengarajan

Jeffrey Charles Herbert

Vipin Aryamvalli

Sahadevan A Kumaran

Sanjay Kumar Mishra

Venkateswara Reddy Konudula

Biswa Bhusan Sahoo

Sumith Kaippalathingal Soman

Sathisha Nanjunde Gowda

In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations.

Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement

A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.

Memory device with separately controlled sense amplifiers

In one embodiment, a self-timed, dual-rail SRAM includes a self-timing circuit having a logic gate that is powered by voltage VDD and configured to receive a fire-sense-amplifier timing signal and to produce a VDD-domain sense-amplifier-enable signal SOELV. The self-timing circuit includes an inverting level-shifter having complementary N-type and P-type transistors connected in series between voltage VDDA and ground. The N-type transistor's gate is connected to signal SOELV, and both transistors' drain terminals are connected together to produce output signal SOEHVB. The inverting level-shifter also includes two series-connected P-type transistors connected (i) between supply voltage VDDA and the output and (ii) in parallel with the first P-type (pull-up) transistor. An inverter is connected between the output node and the control terminal of one of the series transistors, and the other series-transistor's gate is connected to signal SOELV. Thus, the series transistors provide a rapid latching and latch-breaking function.

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail SRAM memories

A memory array is divided into multiple segments, each segment having one or more rows of bitcells. Each segment has control circuitry that controls whether the segment is in an active mode or a power-saving, sleep mode. The control circuitry ensures that a segment transitions from sleep mode to active mode before a row of the segment is accessed by driving a corresponding wordline high. The control circuitry also ensures that, at the end of a row access, the wordline is driven low before the corresponding segment is transitioned from active mode to sleep mode.

Segmented memory having power-saving mode

A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

Memory device with control circuitry for generating a reset signal in read and write modes of operation

A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.

Dual rail power supply scheme for memories

A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality

A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Memory device with area efficient power gating circuitry

A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.

Memory device with trimmable power gating capabilities

A pre-decoded address is generated at a high speed in a semiconductor memory device. The device comprises a pre-decoder () for generating a first pre-decoded address (PDA) by pre-decoding the input address (ADD), a CAM circuit () for activating the match signal (MT) by responding to the indication of a defective memory cell by the input address (ADD), a ROM circuit () for outputting a second pre-decoded address (PDA) and an enable signal (ES) in response to the activation of the match signal (MT), and a multiplexer () for selecting either the first or second pre-decoded address (PDAor PDA) on the basis of the enable signal (ES). According to the present invention, there is no need to use a circuit with numerous stages as there is in substituted logic; accordingly, pre-decoded addresses can be generated at a high speed.

Semiconductor memory device that can relieve defective address

An SRAM cell has reduced gate and sub-threshold leakage currents. The SRAM cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the SRAM cell. The transistors lower the effective supply voltage at different nodes, when either bit '' or '' is stored in the SRAM cell. The reduced effective supply voltage is passed to other coupled transistors for minimizing leakages. The SRAM cell operates in an active mode and dissipates no dynamic power during active mode to inactive mode transition and vice-versa operations. The SRAM cell is also capable of reducing bit line leakage currents under suitable conditions.

8-T SRAM cell circuit, system and method for low leakage current

A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit includes a first discharge device and a second discharge device operatively coupled to the first inverter circuit and the second inverter circuit respectively. The amplifier circuit further includes a first PMOS transistor operatively coupled between the first discharge device and a bit line, and a second PMOS transistor operatively coupled between the second discharge device and a complementary bit line. The amplifier circuit further includes a first NMOS transistor operatively coupled between the first discharge device and a ground voltage, a second NMOS transistor operatively coupled between the second discharge device and the ground voltage. The amplifier further includes a pull down circuit and a delay circuit. The delay circuit produces delay between two control signals. The circuit includes a first NOT gate and a second NOT gate operatively coupled to a first latch output node and a second latch output node respectively to provide an output data corresponding to a data stored in a memory cell.

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Bengaluru, India

Ankur Goel