Samsung Electronics Co., Ltd.

Ankur Ghosh

Tamal Das

Sumanth Chakkirala

Umamaheswara Reddy Katta

Praveen Rathee

Vishal Khatri

An electronic device and a method of controlling a slew rate for high-speed data communications are provided. The electronic device, according to an embodiment of the disclosure, includes a serializer configured to receive parallel data from another electronic device along with clock rate information, and convert the parallel data into serial data. The electronic device further includes a delay generator configured to generate a delay in the converted serial data using the clock rate information. The electronic device further includes a multiplexer configured to multiplex the converted serial data of the non-slew mode with the delayed data of the slew mode. The electronic device further includes a plurality of driver legs configured to receive the multiplexed data, and transfer the multiplexed data to the another electronic device. The electronic device further includes at least one of a voltage-controlled oscillator and a current-controlled oscillator configured to generate the clock rate information.

Electronic device and method for controlling slew rate for high-speed data communications

Methods and systems for selecting voltage for a substrate connection of a bypass switch include a bulk voltage generation circuit coupled externally to the regulator. The bulk voltage generation circuit is configured to control selection of a voltage from among an Input/Output (I/O) supply voltage and a core supply voltage for a substrate connection of a bypass switch of the regulator. The bulk voltage generation circuit is configured to select the voltage for the substrate connection of the bypass switch based on a mode of operation of the regulator and at least one of a presence or an arrival sequence of the I/O supply voltage and the core supply voltage.

Methods and systems for selecting voltage for a substrate connection of a bypass switch

A level shifter includes main and auxiliary level shifters, a switch circuit and a hold circuit. The main level shifter includes NMOS and PMOS transistors in a Differential to Single Ended (D2S) structure. The auxiliary level shifter is connected to an output of the main level shifter and includes NMOS and PMOS transistors. Each of the main and auxiliary level shifters includes internal nodes. The switch circuit settles first nodes of the internal nodes to values to support high speed data transmission, and the hold circuit holds second nodes of the internal nodes to a certain value during low frequency operation. The level shifter receives a serial stream of binary values of core supply voltage, converts the serial stream of binary values from the core supply voltage to an input/output (I/O) voltage, and outputs the serial stream of binary values of the input/output (I/O) voltage.

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Kolkata, India

Ankur Ghosh