Arizona State University

Ankit Wagle

Sarma Vrudhula

A system and method for clock distribution in a digital circuit. In some embodiments, the method, includes: modifying a synchronous digital logic circuit, the modifying including: replacing a first D flipflop in the circuit with a local-clocking source flipflop; and connecting a clock output of the local-clocking source flipflop to a clock input of a second D flipflop, wherein the replacing and connecting increases an objective function, the objective function being based on the number of high drive strength cells in a logic cone preceding the second D flipflop.

System and method for clock distribution in a digital circuit

A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.

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Tempe, AZ, United States of America

Ankit Wagle