Qualcomm Incorporated

International Business Machines Corporation

Ankit Srivastava

Xiaohong Quan

Sameer Wadhwa

Seyed Arash Mirhaj

Robert J Gauthier, Jr

JunJun Li

Eugene Robert Worley

Guoqing Miao

Matthew David Sienko

Xuhao Huang

Jingxue Lu

William Martin Snelgrove

Peter J Shah

Vijayakumar Dhanasekaran

Ren Li

Mohamed Ahmed

Dustin Tarl Dunwell

Manu Mishra

Ayaz Hasan

Matthew David James

Zhongze Wang

Sheng Zhang

Seyfollah Seyfollahi Bazarjani

Xiaonan Chen

Mustafa Keskin

Song Shi

Meysam Azin

Haibo Fei

Xinwang Zhang

Suren Mohan

Le Wang

Shunxi Wang

Mingliang Wang

Seyfi Bazarjani

A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

Charge-pump-based current-mode neuron for machine learning

Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

Sparsity-aware compute-in-memory

Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

Analog adders for multi-bit MAC arrays in reconfigurable analog based neural networks

A multiply-and-accumulate (MAC) circuit having a plurality of compute-in-memory bitcells is configured to multiply a plurality of stored weight bits with a plurality of input bits to provide a MAC output voltage. A successive approximation analog-to-digital converter includes a capacitive-digital-to-analog-converter (CDAC) configured to subtract a bias voltage from the MAC output voltage to provide a CDAC output voltage. A comparator compares the CDAC output voltage to a fixed reference voltage.

Power-efficient compute-in-memory pooling

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

Low-power compute-in-memory bitcell

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

Compute-in-memory bitcell with capacitively-coupled write operation

A near memory system is provided for the calculation of a layer in a machine learning application. The near memory system includes an array of memory cells for storing an array of filter weights. A multiply-and-accumulate circuit couples to columns of the array to form the calculation of the layer.

Power efficient near memory analog multiply-and-accumulate (MAC)

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Compute-in-memory with ternary activation

A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.

Time-shared compute-in-memory bitcell

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a positive capacitor. A first plate of the positive capacitor connects to a positive read bit line. An inverter inverts a voltage of the second plate of the positive capacitor to drive a first plate of a negative capacitor having a second plate connected to a negative read bit line.

Differential compute-in-memory bitcell

A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.

Power-efficient compute-in-memory analog-to-digital converters

A compute-in-memory dynamic random access memory bitcell is provided that includes a first transistor having an on/off state controlled by a weight bit stored across a capacitor. The first transistor is in series with a current-source transistor connected between the first transistor and a read bit line. An activation voltage controls whether the current-source transistor conducts a current when the first transistor is in the on state.

Compute-in-memory dynamic random access memory

In some aspects of the present disclosure, a touch-panel interface includes a plurality of receivers, wherein each of the receivers is coupled to one or more receive lines of a touch panel, and each of the receivers includes a switch capacitor network and an amplifier. The touch-panel interface also includes controller configured to control switches in the switch capacitor network of each of one or more of the receivers to operate each of the one or more of the receivers in one of a plurality of different receiver modes.

Highly configurable front end for touch controllers

Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a passive gain scaling architecture. Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a plurality of capacitive elements, a plurality of switches coupled to the plurality of capacitive elements, and SAR logic having an output coupled to control inputs of the plurality of switches. The circuit also includes a comparator having an output coupled to an input of the SAR logic, a sampling circuit coupled to an input node of the circuit, and a first capacitive element coupled in series between the sampling circuit and the plurality of capacitive elements.

Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling

In some aspects of the present disclosure, a method for touch-panel processing is provided. The method includes receiving a plurality of sensor signals from a touch panel, wherein each one of the plurality of sensor signals corresponds to a respective one of a plurality of channels of the touch panel. The method also includes, for each one of the received sensor signals, converting the received sensor signal into one or more respective digital values. The method further includes, for each one of the received sensor signals, performing digital processing on the one or more respective digital values using a respective one of a plurality of processing engines to generate one or more respective processed digital values. The method further includes performing additional processing on the processed digital values.

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San Diego, CA, United States of America

Ankit Srivastava