Cadence Design Systems, Inc.

Ankit Sethi

Naresh Kumar

Sushobhit Singh

Arvind Nembili Veeravalli

Umesh Gupta

Beenish

Marut Agarwal

Shubham Kumar

Prashant Sethia

Satyendra Patel

Mahesh Diwakar Sadhankar

The present disclosure relates to a system and method for electronic design automation. Embodiments may include loading one or more libraries, netlists, or constraints associated with an electronic design and loading parasitic data associated with the electronic design. Embodiments may further include performing a self adaptive, infinite depth, path based analysis on at least a portion of the electronic design. Embodiments may also include analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis.

Adaptive path based analysis process

Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

System and method for performing sign-off timing analysis of electronic circuit designs

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Delhi, India

Ankit Sethi