Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (Singapore) Pte. Ltd.

Ankit Sajjan Kumar Bansal

Eric Baden

Michael Lau

Eugene Opsasnick

Manoj Lakshmygopalakrishnan

Mark Fairhurst

Yehuda Avidan

Ari Aravinthan

Noam Halevy

Eugene N Opsasnick

Michael H Lau

In the subject system for a network switch may receive one or more packets via a set of input ports. The network switch may write the one or more packets into an ingress buffer of an ingress tile shared by the set of input ports. The network switch may read the one or more packets from the ingress buffer according to a schedule by a scheduler. The network switch may forward the read one or more packets to a plurality of output ports.

Traffic management for high-bandwidth switching

In the subject system for a network switch may determine to transition the output port of the network switch between a store-and-forward (SAF) state and a cut-through (CT) state based on at least one factor. The network switch may determine, based on a condition of the output port, whether to transition the output port to a transition-cut-through (TCT) state or directly to a CT state when transitioning the output port to the CT state. When the output port is transitioned to the TCT state, the network switch may determine, based on the condition of the output port, whether to transition the output port to the CT state or to transition the output port back to the SAF state.

The present disclosure describes a wired communication device having media access control (MAC) circuitry and physical layer (PHY) circuitry. The MAC circuitry frames one or more data packets in accordance with a wired communication standard or protocol to provide one or more data frames. The one or more data frames include one or more packets that are separated by interpacket gaps (IPGs). The MAC circuitry selectively choses a duration of the IPGs to maintain an average IPG duration. The PHY circuitry encodes the one or more data frames in accordance with a line coding scheme that is efficiently represents different possible combinations for types of characters present in the one or more data frames.

Apparatus and method for wired data communication

A device implementing a forward error correction data transmission system may include at least one processor circuit. The at least one processor circuit may be configured to perform line encoding on a data stream received from a media access control (MAC) module, and periodically insert alignment markers after every number of blocks of the data stream, where the alignment markers are determined based at least in part on a data rate of an associated port. The at least one processor circuit may be further configured to transcode the data stream, where each alignment marker remains contiguous in the transcoded data stream. The at least one processor circuit may be further configured to add parity information to the transcoded data stream. The at least one processor circuit may be further configured to transmit the transcoded data stream over at least one physical lane of the associated port.

Forward error correction (FEC) data transmission system

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San Jose, CA, United States of America

Ankit Sajjan Kumar Bansal