Stmicroelectronics International N.v.

Rovi Guides, Inc.

Ankit Gupta

Vikram Makam Gupta

Vishwas Sharadanagar Panchaksharaiah

Anand Kumar

Prashutosh Gupta

Nitin Kumar Gupta

Kallol Chatterjee

Gagan Midha

Sagnik Mukherjee

An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

Pulse width modulator with reduced pulse width

A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

High performance phase locked loop for millimeter wave applications

A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.

A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

Fractional-N phase lock loop (PLL) with noise cancelation

A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.

Phase lock loop (PLL) with operating parameter calibration circuit and method

A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.

Charge pump phase locked loop with low controlled oscillator gain

A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.

Process compensated gain boosting voltage regulator

Systems and methods are described herein for tagging images for placement in a graphical layout based on image characteristics. The overall brightness of an image is determined and, if the overall brightness is below a threshold level of brightness, the image is tagged with a negative identifier indicating that the image cannot be dimmed. If the overall brightness exceeds the threshold level of brightness, then the image is tagged with a positive identifier indicating that the image can be dimmed. Similarly, the resolution of the image is determined and, if the resolution currently affects the image, the image is tagged with a negative identifier indicating that the image cannot be blurred. If the resolution does not affect the image, and further blurring will not affect the image, then the image is tagged with a positive identifier indicating that the image can be blurred.

Systems and methods for tagging images for placement in portions of a graphical layout based on image characteristics

Systems and methods are described herein for tagging images for placement in a graphical layout based on characteristics of depicted faces. The brightness of each face depicted is determined and, if the brightness of any face is below a threshold level of brightness, the image is tagged with a negative identifier indicating that the image cannot be dimmed. If the brightness of every face exceeds the threshold level of brightness, then the image is tagged with a positive identifier indicating that the image can be dimmed. The resolution of the image is also determined and, if the resolution currently affects any face, the image is tagged with a negative identifier indicating that the image cannot be blurred. If the resolution does not affect any face, and further blurring will not affect any image, then the image is tagged with a positive identifier indicating that the image can be blurred.

Systems and methods for tagging images for placement in portions of a graphical layout based on relative characteristics of depicted faces

Systems and methods are described herein for selection of tagged images to populate the graphical layout. The system accesses a layout that defines a plurality of portions of the graphical layout and corresponding image parameters for each portion of the graphical layout. The system selects a first portion of the plurality of portions and retrieves the corresponding image parameters. If the image parameters indicate that the selected portion of the graphical layout is subject to a visual effect, the system selects an image having image parameters, such as the tags described above, indicating that the image can be placed in a portion of the graphical interface which will be subject to the particular visual effect. Otherwise, the system selects an image having image parameters that match the image parameters corresponding to the selected portion of the graphical interface.

Systems and methods for selecting images for placement in portions of a graphical layout

Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.

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Delhi, India

Ankit Gupta