Stmicroelectronics International N.v.

Synopsys, Inc.

Ankit Agrawal

Anand Kumar

Nitin Bansal

Paras Garg

Manish Garg

Sandeep Kaushik

Sayan Adhikary

A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate limited voltage signals, each of which is a fraction of voltage between the pad and supply voltage or between the pad and ground. The NMOS clampers and PMOS clampers configured to receive reference voltages and limited voltage signals to generate output, which is in turn input into gate terminals of the subset of NMOS or PMOS transistors.

High-voltage IO drivers

Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

Low current, wide range input common mode LVDS receiver devices and methods

A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.

Loop independent differential hysteresis receiver

Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

Dual gate FD-SOI transistor

A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

Methodology to avoid gate stress for low voltage devices in FDSOI technology

An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (FDSOI) technology. By enhancing the performance of the NMOS and devices within the level shifting circuit, the Vof the dual gate FDSOI NMOS transistors is lowered without a need for additional control circuitry. Lowering the Vcan be accomplished through dynamic secondary gate control, by coupling together primary and secondary gates of the NMOS devices, while secondary gates of the PMOS devices can be coupled to a high voltage supply level. Such high performance NMOS devices can then operate at higher frequencies and run on a much wider range of core power supplies. Meanwhile, conventional DC conditions are maintained during steady state operation. Because no components are added to the level shifter circuit, the higher performance is achieved without an increase in size and current consumption.

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Greater Noida, India

Ankit Agrawal