Texas Instruments Corporation

Anjana Ghosh

Masashi Hashimoto

Srinath Mathur Ramaswamy

Indu Prathapan

Sundarrajan Rangachari

Himamshu Gopalakrishna Khasnis

Ranjit Kumar Dash

Srinivasan Venkataraman

Sankar Prasad Debnath

Krishnan Ramabhadran

Manoj S Soman

Diganta Baishya

An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks

A method for transfer of digital data, comprising a succession of one values and zero values, across a capacitive interface. The interface includes a first capacitor and a second capacitor in parallel, linking a first circuit to a second circuit. First digital data is transferred from the first circuit to the second circuit, and a reference clock is provided by the first circuit and transmitted with the first data to the second circuit for recovery thereby. A first set of bi-level signals representing the zero values of the first data is applied to the first capacitor, such that a repeating level transition of the reference clock corresponds to a first level transition of the first set of bi-level signals. A second set of bi-level signals representing the one values of the first data is applied to the second capacitor, such that the repeating transition of the reference clock corresponds to a second level transition of the second set of bi-level signals. The clock and data are then recovered.

Capacitive data and clock transmission between isolated ICs

In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

Apparatus and method for transistor element reduction in circuits

In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.

Apparatus and method for a read-modify-write operation in a dynamic

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Bengaluru, India

Anjana Ghosh