Adaptec, Inc.

Ikoa Corporation

Anjan Mitra

Shridhar K Mukund

Mahesh Gopalan

Clement Leung

Manish Mahajan

Vasantha Srirambhatla

Jed Krohnfeldt

Tvp Kameswar Rao

A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable, in-memory processing semiconductor device

An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data paths. The plurality of access data paths are also configurable for a write access from one of the plurality of access data paths. The multi-level array is capable of being configurable into logical partitions with arbitrary starting addresses. The apparatus further includes a compute element in communication with the multi-level array over the plurality of access data paths, the compute element configured to issue a plurality of memory accesses to the multi-level array through the plurality of access data paths. Methods for programming a multi-level array of storage cells and for processor design are also provided.

Apparatus for performing computational transformations as applied to in-memory processing of stateful, transaction oriented systems

A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems

A method for efficiently processing layers of a data packet is provided. The method initiates with defining a pipeline of processors communicating with a distributed network and CPU of a host system. Then, a data packet from the distributed network is received into a first stage of the pipeline. Next, the data packet is processed to remove a header associated with the first stage. Then, the processed data packet is transmitted to a second stage. The operations of processing and transmitting the processed data packet are repeated for successive stages until a header associated with a final stage has been removed. Then, the data packet is transmitted to the CPU of the host system. It should be appreciated that the header is not necessarily transformed at each stage. For example, suitable processing that does not strip the header may be applied at each stage.

Method and apparatus for a pipeline architecture

A method and apparatus for performing a cyclic redundancy check (CRC) process is provided. The CRC is capable of being performed on data received out of order without having to store and assemble the data. One exemplary method for computing a CRC for a transmitted data stream initiates with performing a CRC process on a first segment of the data stream to generate a first CRC remainder. Next, the first CRC remainder for the first segment is projected. Then, the CRC process on a second segment of the data stream is performed to generate a second CRC remainder. Next, the second CRC remainder for the second segment is projected. Then, the projected remainders are combined to calculate a complete CRC remainder for the data stream in an order independent fashion. Data streams including multiple segments can be handled by the CRC process.

Separable cyclic redundancy check

A network interface card is provided. The network interface card includes a plurality of pipelined processors. Each of the pipelined processors includes an input socket having at least three single ported memory regions configured to store variable-size data packets. The at least three single ported memory regions enable a downstream processor reading the variable-size data packets from the single ported memory regions to maintain a data throughput to support an incoming line rate of a data stream. The line rate data throughput is maintained after a maximum size data packet has been read by the downstream processor. Methods of method for optimizing throughput between a producing processor and a consuming processor and a processor are also provided.

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Santa Clara, CA, United States of America

Anjan Mitra