Intel Corporation

Anitha Loke

Fabrice Paillet

Jason Seung-Min Kim

Kursad Kiziloglu

Nitin N Garegrat

Andrew Yang

Nasima Parveen

David Y Fang

Dmitry Sergeyevich Lukiyanchenko

Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

Proactive Di/Dt voltage droop mitigation

Growing community of inventors

Santa Clara, CA, United States of America

Anitha Loke