Lsi Logic Corporation

Lsi Corporation

Anita Greeb

Kevin J Gearhardt

Doug Feist

A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.

Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices

A measurement technique which allows the error components of the testing process to be eliminated by performing a differential-style measurement of the programmable termination resistor network. Since for any given DUT pin which is to be tested, there are multiple possible resistances to be measured, the test process provides that two or more resistance measurements are taken on the same pin. Once those values containing the error components are obtained, they are compared to generate a differential resistance measurement which contains only the actual on-chip DUT resistance with the error components completely removed. The differential value can then be tested against previously defined test limits that are set to guarantee the conformance of the on-chip resistance to the processing specifications. The technique can be applied at either the wafer sort or package test phase of device testing, with the different error components associated with either phase being eliminated.

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Anita Greeb