Cadence Design Systems, Inc.

Anish Mathew

Sandeep Brahmadathan

Bikram Banerjee

Gopi Krishnamurthy

Anujan Varma

Steven Ho

Chetan Paragaonkar

Raveendra Pai Gopalakrishna

Raveendra Pai G

A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of each of the encrypted data blocks.

Device and method for low-latency and encrypted hardware layer communication

Embodiments disclosed are directed to methods for scheduling packets. According to example embodiments the method includes receiving, using a first layer in a communication protocol, a first request from a second layer in the communication protocol. The first request indicates to the first layer to output a data stream that includes a first location for the second layer to include a first control packet. The first layer is at a higher level of abstraction than the second layer. The method further includes transmitting, using the first layer, a first response to the second layer. The first response is based on the first request, and the first response identifies the first location in the data stream and a time of occurrence of the first location in the data stream.

Hardware-efficient scheduling of packets on data paths

Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and completion TLPs. PCI implementations may further include an identification-based ordering mechanism to revise the order. The methods identify a completion TLP and multiple posted TLPs, associate a posted TLP with an ordering token, and determine the order for handling the completion and posted TLPs with at least the pointer-based ordering mechanism. The methods may further optionally revise the order with at least the identification-based ordering mechanism.

Methods, systems, and computer program product for a PCI implementation handling multiple packets

A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.

System and method for expeditious transfer of data from source to destination in error corrected manner

A programmable sequence generator for controlling a flash memory device. The programmable sequence generator includes a plurality of programmable sequence registers including control phase sequence (CPS) registers and data phase sequence (DPS) registers programmed with phase sequence values corresponding to an operation command sequence of the flash memory device; and logic circuitry in a programmable command sequencer for controlling a set of states of the programmable command sequencer using the plurality of programmable sequence registers.

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Kerala, India

Anish Mathew