Western Digital Technologies, Inc.

Micron Technology Incorporated

Hgst Netherlands, B.v.

Aniryudh Reddy Durgam

Aldo Giovanni Cometti

Haritha Uppalapati

Sivagnanam Parthasarathy

Saeed Sharifi Tehrani

Dillip Kumar Dash

Kiran Yalamanchi

Exemplary methods, apparatuses, and systems include receiving a read operation directed to an aggressor location. An integrity scan of a victim location of the aggressor location is performed to determine an error value for the victim location. Data from the aggressor location is copied to a cache in response to determining the error value for the victim location satisfies a first error value threshold. The cache is a different type of memory from the aggressor location.

Identification and caching of frequent read disturb aggressors

A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.

Code rate switching mechanism for data storage system

Code rate switching mechanism for flash memory

A method for managing a flash storage system includes measuring an operation time to complete a data operation on a flash memory block of a flash memory device of the flash storage system. The method includes updating, based on the measured operation time, a running average time for the flash memory device to complete the data operation. The method includes comparing the updated running average time to a threshold time. The method includes adjusting an operating parameter for the flash memory device to perform the data operation based on the comparison.

Continuous adaptive calibration for flash memory devices

A storage device may include a controller and a plurality of memory devices logically divided into a plurality of pages. Each page in the plurality of pages may include a plurality of bits. The controller may be configured to: apply a read level to a control gate of a transistor for each respective bit in the plurality of bits; determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits; determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value; and adjust, based on the error ratio, the read level.

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San Diego, CA, United States of America

Aniryudh Reddy Durgam