Intel Corporation

Aniruddha Vaidya

Akhilesh Kumar

Mani Azimi

Ioannis T Schoinas

Anahita Shayesteh

Mani Ayyar

Rama R Menon

Dongkook Park

Dong Hyuk Woo

Saikat Saharoy

Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5&#xd7;5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.

Modular decoupled crossbar for on-chip router

In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.

Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor

An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.

Conditional and vectored system management interrupts

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Sunnyvale, CA, United States of America

Aniruddha Vaidya