Nxp Usa, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Anirban Roy

Michael Alan Sadd

Jon Scott Choy

Nihaar N Mahatme

Perry H Pelley

Mark Douglas Hall

Tushar Praful Merchant

Frank Kelsey Baker, Jr

Richard Eguchi

Thomas Jew

Craig T Swift

Ko-Min Chang

Padmaraj Sanjeevarao

Jacob Williams

Bruce L Morton

Anis Mahmoud Jarrar

David B Kramer

Kerry A Ilgenstein

Gayathri Bhagavatheeswaran

Michiel Jos Van Duuren

Uzi Zangi

Guido Jozef Maria Dormans

Craig A Cavins

Yanzhe Tang

Tom D Vo

Melvin Guison Mangibin

Frank Kelly Baker, Jr

Thomas Stephen Harp

Maryfe Hernandez

An integrated circuit DAC device and fabrication method are provided with a linear bias ladder circuit which generates a plurality of bias voltages, an inverting operational amplifier configured to generate an analog output voltage in response to an input current signal, and a plurality of MMT devices connected between the linear bias ladder circuit and the inverting operational amplifier to implement a DAC with a first current control gate of each MMT device connected to one of the plurality of N different bias voltages, with a second switch control gate of each MMT device connected to receive one of a plurality digital input code values, with a drain terminal of each MMT device connected to a digital bias voltage (Vdbias), and with a source terminal of each MMT device connected to provide the input current signal to the inverting operational amplifier.

DAC and ADC using MMT devices

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

Refresh operations in embedded dynamic random access memories (DRAMs)

A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

Memory with one-time programmable (OTP) cells

A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.

Magnetoresistive random access memory (MRAM) with end of life margin sensor

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form first remnant silicon germanium nanosheet layers () in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG) and to form second remnant silicon germanium nanosheet layers () in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Nanosheet device with different gate lengths in same stack

An array of bit cells is programmed with user data, each row including a corresponding word line and each column including a corresponding column line. The array includes a plurality of differential PUF bits, each having a first and second bit cell programmed with user data. A first set of sense-amplifiers outputs a set of data bits of the user data, and a second set of sense-amplifiers outputs a set of differential bits, each differential bit based on a differential current between two columns lines of the selected column lines corresponding to the first and second bit cells of a corresponding differential PUF bit along the selected word line. A potential PUF bit generator outputs a set of potential PUF bits based on the set of data bits of the user data from the first set of sense-amplifiers and the set of differential bits from the second set of sense-amplifiers.

Reusing memory arrays for physically unclonable function (PUF) generation

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (--) which are separated from one another by a barrier oxide layer () and which are separately processed to form bottom gate electrodes having a first gate structure (A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (A-B) in the top Si/SiGe superlattice structures.

Nanosheet transistors with different gate materials in same stack and method of making

A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors () and capacitors/sensors () in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (A-A,B-B) which are selectively processed to form gate electrode structures (A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (C,C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (C,C,C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g.,-) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g.,--) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

Method of making nanosheet fringe capacitors or MEMS sensors with dissimilar electrode materials

A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.

Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMS)

A nanosheet MEMS sensor device and method are described for integrating the fabrication of nanosheet transistors () and MEMS sensors () in a single nanosheet process flow by forming separate nanosheet transistor and MEMS sensor stacks (A-A,B-B) of alternating Si and SiGe layers which are selectively processed to form gate electrodes (A-C) which replace the silicon germanium layers in the nanosheet transistor stack, to form silicon fixed electrodes using silicon layers (B-B-) on a first side of the MEMS sensor stack, and to form silicon cantilever electrodes using silicon layers (B-B-) on a second side of the MEMS sensor stack by forming a narrow trench opening () in the MEMS sensor stack to expose and remove remnant silicon germanium layers on the second side in the MEMS sensor stack.

Nanosheet MEMs sensor device and method of manufacture

A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.

Temperature exposure detection based on memory cell retention error rate

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (-) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (A,B) and to form gate electrodes (A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g.,) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

Method of making nanosheet local capacitors and nvm devices

A memory includes an array of resistive memory cells and circuitry for setting a write parameter for improving write effectiveness to the cells of the memory array. The circuitry performs a write parameter setting routine that determines a midpoint resistance of a memory state of cells of the array and determines a write efficiency of a weak write operation to cells of the array. Based on the determined midpoint resistance and the determined write efficiency, the circuit sets a write parameter level for subsequent writes to cells of the array.

Resistive memory with adjustable write parameter

Error rate reduction in a non-volatile memory (NVM), including magneto-resistive random access memories (MRAMs)

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.

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Austin, TX, United States of America

Anirban Roy