Xilinx, Inc.

Splunk Inc.

Anirban Rahut

Sudip K Nag

Raymond Kong

Jason Helge Anderson

Sundar Vasan

Sankaranarayanan Srinivasan

Vinay Verma

Kamal Chaudhary

Sridhar Krishnamurthy

Brian Philofsky

Rajeev Jayaraman

Hasan Arslan

Arifur Rahman

Srinivasan Dasasathyan

Sandor S Kalman

Satyaki Das

Krishnan Anandh

Hui Xu

Meng Lou

Systems and methods for search result replication in a search head cluster of a data aggregation and analysis system. An example method may include receiving, by a search head leader of a search head cluster including multiple search heads, from a first search head of the plurality of search heads, a search result in response to a search query. The search head leader parses a registry comprising a set of replicas of the search result in the search head cluster to determine a replication count corresponding to a number of replicas of the search result. A determination is made that the replication count is greater than a target replication count. Based on the determination, a selected replica from the set of replicas is identified based at least in part on a recency of use of the selected replica and a deletion of the selected replica is initiated.

Search result replication management in a search head cluster

Systems and methods for search result replication in a search head cluster of a data aggregation and analysis system. An example method may comprise maintaining a replication count in a data store associated with at least one of the plurality of search heads, the replication count corresponding to how many of the replicas of the search result are stored in the search head cluster, determining that the replication count is greater than a target replication count, based on determining that the replication count is greater than the target replication count, initiating a deletion of at least one replica of the replicas of the search result from a target search head of the plurality of search heads storing the replicas, receiving an indication that the deletion is complete, and based on receiving the indication that the deletion is complete, decreasing the replication count corresponding to the search result.

A high availability scheduler of tasks in a cluster of server devices is provided. A server device of the cluster of server devices enters a leader state based upon the results of an election process in which the server device participates with others of the cluster of server devices. Upon entering the leader state, the server device schedules one or more tasks by assigning each of the one or more tasks to a device, wherein the one or more tasks involve initiating a search of time stamped events.

High availability scheduler for scheduling map-reduce searches based on a leader state

Systems and methods for search result replication in a search head cluster of a data aggregation and analysis system. An example method may comprise maintaining a replication count corresponding to how many replicas of a result of a particular map-reduce search exist in a search head cluster comprising a plurality of search heads that are each configured to enable them to manage a reduce phase of a map-reduce search, determining that the replication count is less than a target replication count, selecting, based the determining, a target search head from the search head cluster to receive a replica of the search result, initiating a replication of the search result from a source search head in the search head cluster to the selected target search head, receiving an indication that the replication is complete, and based on receiving the indication, increasing the replication count corresponding to the search result.

Search result replication in a search head cluster

A high availability scheduler of tasks in a cluster of server devices is provided. A server device of the cluster of server devices enters a leader state based upon the results of a consensus election process in which the server device participates with others of the cluster of server devices. Upon entering the leader state, the server device schedules one or more tasks by assigning each of the one or more tasks to a device, wherein the one or more tasks involve initiating a search of time stamped events.

High availability scheduler for scheduling searches of time stamped events

A high availability scheduler of tasks in a cluster of server devices is provided. A server device of the cluster of server devices enters a leader state based upon the results of a consensus election process in which the server device participates with others of the cluster of server devices. Upon entering the leader state, the server device schedules one or more tasks by assigning each of the one or more tasks to a device, wherein the one or more tasks involve initiating a late-binding schema.

High availability scheduler for scheduling map-reduce searches

A high availability scheduler of tasks in a cluster of server devices is provided. A server device of the cluster of server devices enters a leader state based upon the results of a consensus election process in which the server device participates with others of the cluster of server devices. Upon entering the leader state, the server device schedules one or more tasks by assigning each of the one or more tasks to a server device in the cluster.

High availability scheduler

A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

Latch based optimization during implementation of circuit designs for programmable logic devices

A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Run-time efficient methods for routing large multi-fanout nets

A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Method and apparatus for selecting programmable interconnects to reduce clock skew

Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.

Patterns for routing nets in a programmable logic device

Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.

Methods of estimating net delays in tile-based PLD architectures

Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

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Santa Clara, CA, United States of America

Anirban Rahut