Western Digital Technologies, Inc.

Anindya Rai

Jameer Mulani

Kapil Sundrani

Devanathan Balasundaram

Saugata Das Purkayastha

A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Distribution of logical-to-physical address entries across multiple memory areas

Distribution of logical-to-physical address entries across bank groups

Apparatuses and techniques are provided for switching a solid-state device (SSD) between a traditional SSD mode and an open-channel SSD (OCSSD) mode. In one aspect, a set of commands are defined for communicating different types of data from a Flash Translation Layer (FTL) between the host and SSD. The commands can include different predetermined sets of bits which carry different types of FTL data in a standardized format. The commands can be transmitted using reserved data words in an interface specification which interfaces the host to the SSD. The commands can include commands to transfer a logical-to-physical address table, a validity bitmap and a wear table. A switch mode command can include a bit indicating whether the mode is to be switched from traditional SSD to OCSSD, or from OCSSD to traditional SSD.

Method to switch between traditional SSD and open-channel SSD without data loss

A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.

System and method to improve input output command latency by dynamic size logical to physical caching

Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.

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Bengaluru, India

Anindya Rai