Cirrus Logic Inc.

Anindya Bhattacharya

John L Melanson

Seung Bae Lee

Prashanth Drakshapalli

Bhoodev Kumar

Jing Bai

Jaimin A Mehta

Tim Green

Yongsheng Shi

Christopher M Dougherty

Aleksey Sergeyevich Khenkin

John Christopher Tucker

Stephen Timothy Hodapp

Saurabh Singh

David Paul Singleton

Ruoxin Jiang

Morgan Timothy Prior

David F Cox

Jonathan Timothy Wigner

Roderick D Holley

Jaiminkumar Mehta

Qi Cai

Vaibhav Pandey

Sunny Bhagia

Ying Ou

Sriram Balasubramanian

Johnny Klarenbeek

Jaimin Mehta

Jin Bai

A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Apparatus and methods for detecting a microphone condition

Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

Class D amplifier circuitry

A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS.

Hall sensor-based data acquisition system

Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.

Digital-to-analog conversion architecture and method

A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.

Minimizing artifacts resulting from clock switching of sampled data converters

A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.

Resistive sensor based data acquisition system using low distortion analog front-end and digital gain error correction

A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror. The selectable output current mirror may also include switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch and glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.

Glitch mitigation in selectable output current mirrors with degeneration resistors

In accordance with embodiments of the present disclosure, an apparatus for measuring acceleration may include a spring-mounted mass, a positional encoder configured to measure a position of the spring-mounted mass and output one or more signals indicative of a sine and a cosine of the position, a driver to set and maintain an oscillation of the spring-mounted mass, and a decoder configured to process the one or more signals to calculate an acceleration of the spring-mounted mass.

Systems and methods for determining acceleration based on phase demodulation of an electrical signal

A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.

Systems and methods for peak junction temperature sensing and thermal safe operating area protection

A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than or equal to 2 and wherein the n-stage stacked charging circuit may comprise n&#x2212;1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n&#x2212;1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n&#x2212;1th discharging time period through the respective n&#x2212;1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Stepped voltage drive for driving capacitive loads

A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

High voltage linear amplifier driving heavy capacitive loads with reduced power dissipation

A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than one which may comprise n&#x2212;1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n&#x2212;1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n&#x2212;1th discharging time period through the respective n&#x2212;1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

The system contains a first input receiving a signal from the amplifier input. A second input receives a signal from the amplifier output. A gain modification device is connected to the second input thereby reducing an amplitude of the signal from the amplifier output. A difference element connected to the gain modification device and the first input subtracts one of the first input and the second input from the other of the first input and the second input and outputting a difference voltage. A comparator, connected to the difference element and a threshold voltage source, compares the difference voltage to a threshold voltage. A disabling device is connected to the comparator and an output stage of the amplifier, wherein an output stage of the amplifier is disabled when the threshold voltage exceeds the difference voltage.

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Tucson, AZ, United States of America

Anindya Bhattacharya