Qualcomm Incorporated

Texas Instruments Corporation

Animesh Paul

Xinhua Chen

Jingcheng Zhuang

Frederic Bossu

Ravi Sridhara

Jianyun Hu

An integrated circuit, with an error amplifier having a first input, a second input, and an output, a voltage controlled oscillator having an input coupled to the output of the error amplifier, a feedback controlled voltage stage having at least one control coupled to the output of the error amplifier and an output coupled to the first input of the error amplifier, and an adaptive-reference voltage stage coupled to the second input of the error amplifier.

Reducing target frequency variation in oscillator

In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.

Two point frequency search based PLL control

An oscillator apparatus, including a first node adapted to be coupled to a first terminal of a crystal oscillator; a second node adapted to be coupled to a second terminal of the crystal oscillator; a transconductance circuit; a first switch coupled between the first node and the second node; and a second switch coupled between the transconductance circuit and the second node.

Reducing startup time in a crystal oscillator

In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

Low power 25% duty cycle local oscillator clock generation circuit

A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

PLL post divider phase continuity

Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

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Bengaluru, India

Animesh Paul