Micron Technology Incorporated

Lodestar Licensing Group LLC

Anilkumar Chandolu

Indra V Chary

Darwin A Clampitt

Matthew J King

S M Istiaque Hossain

Prakash Rau Mokhna Rau

Sameer S Vadhavkar

Brett D Lowe

Christopher J Larsen

Arun Kumar Dhayalan

Wayne H Huang

Tom Jibu John

Gordon A Haller

David A Daycock

Xiao Li

Thomas George

Sidhartha Gupta

Kenneth N Hagen

Wesley O McKinsey

John David Hopkins

Lifang Xu

Justin B Dorhout

Roger W Lindsay

Jian Li

Chet E Carter

Albert Fayrushin

Yi Hu

Harsh Narendrakumar Jain

Matthew Park

Damir Fazil

Shawn D Lyonsmith

Merri Lyn Carlson

Justin D Shepherdson

David Daycock

Jun Fang

Kevin Y Titus

Lisa R Copenspire-Ross

Christopher R Ritchie

Raja Kumar Varma Manthena

Joel D Peterson

Martin Jared Barclay

Michael D Kenney

Corey Staller

Kye Hyun Baek

Lisa M Clampitt

Giorgio Mariottini

Rokibul Islam

Pavithra Natarajan

George Matamis

Shuangqiang Luo

Mark Bossler

Kevin R Gast

Shashank Saraf

Mark Bossier

Sm Istiaque Hossain

Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.

Microelectronic devices with lower recessed conductive structures and related methods

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

Electronic devices including pillars in array regions and non-array regions

A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

Microelectronic devices including active contacts and support contacts, and related electronic systems and methods

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

Methods used in forming a memory array comprising strings of memory cells including forming a pair of elevationally-extending walls that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated

An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.

Electronic devices including tiered stacks including conductive structures isolated by slot structures, and related systems and methods

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

Memory device including multiple decks of memory cells and pillars extending through the decks

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.

Integrated circuitry, memory arrays comprising strings of memory cells, methods used in forming integrated circuitry, and methods used in forming a memory array comprising strings of memory cells

An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

Electronic devices comprising memory pillars and dummy pillars including an oxide material, and related systems and methods

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies, and methods of forming integrated assemblies

Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.

Methods and systems for measuring semiconductor devices

An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.

Electronic devices with recessed conductive structures

A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

Apparatuses and memory devices including slot structures extending through stack structures

Some embodiments include a method of forming an integrated assembly. Laterally alternating first and second sacrificial materials are formed over a conductive structure, and then a stack of vertically alternating first and second levels is formed over the sacrificial materials. The first levels include first material and the second levels include insulative second material. Channel-material-openings are formed to extend through the stack and through at least some of the strips. Channel-material-pillars are formed within the channel-material-openings. Slits are formed to extend through the stack and through the sacrificial materials. The first sacrificial material is replaced with first conductive material and then the second sacrificial material is replaced with second conductive material. At least some of the first material of the stack is replaced with third conductive material. Some embodiments include integrated assemblies.

Growing community of inventors

Boise, ID, United States of America

Anilkumar Chandolu