Intel Corporation

Anil Vasudevan

Robert G Blankenship

Debendra Das Sharma

David J Harriman

Mahesh U Wagh

Mark B Rosenbluth

Jasmin Ajanovic

Scott Dion Rodgers

Prashant Sethi

Ilan Pardo

Sridhar Muthrasanallur

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Ohad Falik

Sujoy Sen

Parthasarathy Sarangam

Linden Cornett

Abraham Mendelson

Yadong Li

David B Minturn

Kiran A Patil

Ren Wang

Ilango S Ganga

Avi Mendelson

Alain Gravel

Thomas L Stachura

Partha Sarangam

Radia Joy Perlman

Andrew J Herdrich

Eliezer Tamir

Thomas D Lovett

Hemal Vinodchandra Shah

Hugh Wilkinson

Anshuman Thakur

Jesse C Brandeburg

Gary Tsao

Greg J Regnier

Venkata Krishnan

Raanan Sade

Christopher B Wilkerson

Vedaraman Geetha

Manasi Deval

Shrikant M Shah

Eric K Mann

Chyi-Chang Miao

Binh Q Pham

Marshall A Millier

Avi (Abraham) Mendelson

Arun Chekhov Ilango

Olivier Serres

Tsung-Yuan Charles Tai

Daniel Todd Cohn

D Michael Bell

Ram Huggahalli

Dennis Bell

Glenn J Hinton

Baiju V Patel

Ben-Zion Friedman

Joseph Nuzman

Ziye Yang

Nimrod Diamant

Niall D McDonnell

Dave B Minturn

Samantika S Sury

Namakkal N Venkatesan

Ronen Chayat

Marc Jalfon

Prafulla Deuskar

James R Harris

Benjamin Walker

Ygdal Naouri

Mark W Wunderlich

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Parathasarathy Sarangam

Michael K Cline

Sudheer Mogilappagari

Lawrence Stewart

Christopher B Wilerkson

Antoine Kaufmann

There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.

Application-level network queueing

The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.

Storage transactions with predictable latency

Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

Packet processing with reduced latency

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

Method and system for performing data movement operations with read snapshot and in place write update

Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.

Efficient receive interrupt signaling

A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

Multiple uplink port devices

Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.

Reorder resilient transport

This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.

Ethernet enhancements

Some examples provide for storage of context information in memory in the process of creating a network connection and subsequent availability of the context information. A context address can refer to context for a packet processing path. A host can provide a context address and associated packet characteristics to a network interface device. If the network interface device receives a packet with the characteristics, the context address can be passed to the host and the host can retrieve the context information using the context address.

Availability of context information for packet processing

Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

Software-transparent hardware predictor for core-to-core data transfer optimization

In an example, there is disclosed a computing apparatus, having: a network interface configured to provide a plurality of queues; an application; and one or more logic elements comprising a queuing engine to: inspect an incoming packet; and assign the incoming packet to a dedicated queue for the application based on a classifier. There is also disclosed a method of providing a queuing engine, and one or more tangible, non-transitory computer-readable storage mediums having stored thereon executable instructions for providing a queuing engine.

Growing community of inventors

Portland, OR, United States of America

Anil Vasudevan