International Business Machines Corporation

Anil Shrikant Keste

Tin-Chee Lo

Yuk-Ming Ng

Ashutosh Misra

Jeffrey M Turner

Thomas D Needham

Seetharam Gundu Rao

Krishna M Desai

A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.

Method and system for performing a memory-mode write to cache

A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Sequence alignment logic for generating output representing the slowest from group write slaves response inputs

Slaves with identification and selection stages for group write

A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The apparatus includes a first circuit for generating an address phase for read data coupled to the PLB, and a second circuit for generating an address phase for write data coupled to the PLB. The second address phase generating circuit is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa. The first and second address phase generating circuits can simultaneously process read and write requests. The apparatus also may include circuits for handling read and write data coupled to the first and second address generating circuits, respectively. Further, the apparatus may include circuits for requesting read and write data coupled to the read- and write-data handling circuits, respectively.

Dual master device for improved utilization of a processor local bus

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Bengaluru, India

Anil Shrikant Keste