Avago Technologies General IP (Singapore) Pte. Ltd.

Javelin Semiconductor, Inc.

Anil Samavedam

David E Bockelman

Vishnu Shankar Srinivasan

Eric Kimball

An apparatus comprises an amplifier comprising at least one metal oxide semiconductor (MOS) transistor having a parasitic gate-to-drain capacitance, and at least one MOS neutralization device having a neutralization capacitance configured to compensate for the parasitic gate-to-drain capacitance of the at least one MOS transistor.

Neutralization of parasitic capacitance using MOS device

Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Non-linear capacitance compensation

In one embodiment, a method includes generating a current that is proportional to a mobility and an oxide capacitance of a tracking device and independent of a threshold voltage variation of the tracking device, generating a voltage from the current, and providing the voltage as at least part of a bias voltage for another device. In one embodiment, this other device may be a compensation circuit coupled to a main device to compensate for capacitance non-linearity of the main device.

Growing community of inventors

Austin, TX, United States of America

Anil Samavedam