International Business Machines Corporation

Anil Pothireddy

Brian Thomas Vanderpool

Vibhor K Srivastava

Nikolaos Chrysos

Jayashri Arsikere Basappa

Cyriel Johan Minkenberg

Girish Gopala Kurup

David Grant Wheeler

Ashish A More

Saravanan Sethuraman

Christoph Raisch

Scott Douglas Clark

Jan-Bernd Themann

Sudheendra Srivathsa

Neranjen Ramalingam

Kirtish Karlekar

Claude Basso

Fabrice Jean Verplanken

Jean Louis Calvignac

Daniel Gene Eisenhauer

Mark L Rudquist

Kenneth Pichamuthu

Gopikrishnan Viswanadhan

Baalaji Ramamoorthy Konda

Grant D Wheeler

A method and system are provided for implementing a hierarchical high radix switch with a time-sliced crossbar. The hierarchical high radix switch includes a plurality of inputs and a plurality of outputs. Each input belongs to one input group; each input group sends consolidated requests to each output, by ORing the requests from the local input ports in that input group. Each output port belongs to one output group; each output port grants one of the requesting input groups using a rotating priority defined by a next-to-serve pointer. Each output group consolidates the output port grants and allows one grant to pass back to an input group. Each input port in an input group evaluates all incoming grants in an oldest packet first manner to form an accept. Each input group consolidates the input port accepts and selects one accept to send to the output port.

Implementing hierarchical high radix switch with timesliced crossbar

A method for scheduling a crossbar using distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a switch unit is provided. The switch unit may be a hierarchical high radix switch with a timesliced crossbar that is configured to transfer packets between a plurality of input ports and a plurality of output ports, organized into groups, using wide words. The timesliced crossbar transfers data for a given packet once per supercycle, in a designated timeslice of that supercycle. Multiple buffered packets from one input port to multiple output ports are transferred by utilizing different timeslices of the supercycle.

Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar

Programmable data recorders are provided in a network semiconductor chip to monitor and record all or portions of data from various interfaces, including the input and output interfaces of network links interfacing the chip. A data recorder is provided for each network link. The data recorders store captured data in storage arrays. Data may be compressed and associated with time stamps to conserve space in the storage arrays. A data recorder manager in the chip may start and stop the data recorders at approximately the same time. The programmable mode of the data recorders determines which interfaces are monitored, the portion of data captured, and the format of the data in the storage arrays.

Integrated link-based data recorder for semiconductor chip

Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters in a distributed switch. Input and output ports are grouped and assigned a respective arbiter. The input group arbiters communicate requests indicating a count of respective ports having data packets to be transmitted via one of the output ports. The output group arbiter attempts to accommodate the requests for each member of an input group before proceeding to a next input group.

Weightage-based scheduling for hierarchical switching fabrics

A method includes receiving a first packet at an input of a switching device and determining whether to insert first data associated with the first packet into a normal buffer of the input. The determination of whether to insert first data associated with the first packet into the normal buffer includes determining whether the first output identifier matches a second output identifier corresponding to second data in the normal buffer that is associated with a second packet. The first data is inserted into the normal buffer when the first output identifier matches the second output identifier.

Input buffered switching device including bypass logic

Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.

Translating between an ethernet protocol and a converged enhanced ethernet protocol

Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.

Translation between a first communication protocol and a second communication protocol

Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request.

Cache memory including a predict buffer

A method and system for using a magnitude comparator circuit and a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could otherwise cause the system to hang. Preferably, the flag bit is set with all the valid state transitions, and a magnitude comparator is used to continuously monitor the value of the current state bits. When a FSM state transition occurs based on the flag bit and the output of the magnitude comparator, a potential error condition can be detected and the FSM transition can be blocked or the FSM can be safely transitioned into a predetermined 'reset state'.

Finite state machine error recovery

A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency Cand a second clock domain operating at a second clock frequency C. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C, which, in one embodiment, is greater than and a whole number multiple of C. Preferably, Cis an even whole number multiple of C. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C, and clock signals A and B are source synchronized.

Reducing latency in data transfer between asynchronous clock domains

A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length 'L'. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

Encoding a gray code sequence for an odd length sequence

A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.

In system diagnostics through scan matrix

A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a 'load intensive' device or as a 'store intensive' device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the &#x201c;outbound&#x201d; and &#x201c;inbound&#x201d; buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either &#x201c;load intensive&#x201d; or &#x201c;store intensive&#x201d; mode. The invention is applicable for use with all types of communications network switches (i.e. &#x201c;Bridges&#x201d;, &#x201c;Hubs&#x201d;, &#x201c;Routers&#x201d; etc.).

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Bengaluru, India

Anil Pothireddy