Cadence Design Systems, Inc.

Anil Malik

Sameer Chakravarthy Chillarige

Joseph Michael Swenton

Sharjinder Singh

Krishna Chakravadhanula

Brion L Keller

Gilbert C Vandling

Bharath Nandakumar

Joe Swenton

Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions ('0' to '0', &#x201c;0&#x201d; to &#x201c;1&#x201d;, &#x201c;1&#x201d; to 0&#x201d;, &#x201c;1&#x201d; to &#x201c;1&#x201d;) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.

Scan channel slicing for compression-mode testing of scan chains

Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at least one previously diagnosed electronic device, that the wherein the processor diagnoses defects in one or more of the plurality of electronic devices using the grouped failure data, and that the processor outputs the diagnosis results to the diagnosis results database.

System and method for multiple device diagnostics and failure grouping

A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.

Highly accurate defect identification and prioritization of fault locations

The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

System and method performing scan chain diagnosis of an electronic design

Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary output pins. Embodiments may include performing fault selection on a single core instance for each failure associated with the plurality of core instances and performing fault simulations on the single core instance for each candidate faults associated with the plurality of core instances. Embodiments may include generating fault signatures for each detected fault based upon the instances associated with each detected fault and analyzing each fault signature to determine failure locations.

System and method for diagnosing failure locations in electronic circuits

In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

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New Delhi, India

Anil Malik