Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Anil Kumar

Ankur Bal

Anupam Jain

Rakhel Kumar Parida

Mohit Kaushik

Pratap Narayan Singh

Rakesh Malik

Vivek Tripathi

Puneet Mahajan

Anand Singh Rawat

An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2&#x2212;1, each having a resistance equal to R*(2)*i, i being an index having a value ranging from 1 to 2&#x2212;1, a first of the M resistors having a resistance of R*2, a last of the M resistors having a resistance of R*2*(2&#x2212;1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

On-chip resistor trimming to compensate for process variation

A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2&#x2212;1, with each of the M resistors having a resistance of R*(2)*i, i being an index having a value ranging from 1 to 2&#x2212;1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2&#x2212;1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

Current steering digital to analog converter with decoder free quad switching

A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2&#x2212;1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Glitch free dynamic element matching scheme

A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.

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Greater Noida, India

Anil Kumar