Cadence Design Systems, Inc.

Anil Kumar Mishra

Fangfang Li

Shashank Prasad

Xincheng Zhang

Feng Cheng

Md Shaukat Ullah

Embodiments disclosed herein describe systems, methods, and products for concurrently placing and optimizing input-output (IO) pins and internal components of an integrated circuit (IC) design. In an illustrative process flow, the computer (executing an illustrative EDA tool) may import the IC design and unplace the IO pins of the imported IC design. The computer may set one or more constraints for the IO pins with more degrees of freedom than the conventional pre-fixed locations. The computer may then concurrently place the IO pins and the internal components such that the IO pins obey the one or more constraints. The computer may iteratively optimize the placement of the IO pins and the internal components while ensuring that the one or more constraints are not violated.

Systems and methods of concurrent placement of input-output pins and internal components in an integrated circuit design

The present disclosure relates to a computer-implemented method for assigning pins in an electronic design. The method may include generating a pin list associated with the electronic design, the pin list having a one or more pins that are directly and indirectly connected with at least one of a master partition and a clone partition. The method may further include sorting one or more pins within the pin list based upon, at least in part, a number of local connections to generate a sorted pin list and selecting a first pin having a highest number of local connections of the sorted pin list as a reference pin. The method may also include selecting a partition of the reference pin, as a reference partition and identifying one or more alignment zones for every connected pair of pins in the sorted pin list. The method may further include transforming all alignment zones to the reference partition using a depth-first-search.

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Uttar Pradesh, India

Anil Kumar Mishra