Ampere Computing LLC

Anil Kumar Handenahalli Rajanna

Nagi Aboulenein

Massimo Sutera

Sandeep Brahmadathan

Kha Minh Huynh

Rakesh Kumar

Apparatus and methods for extending functionality of memory controllers using a loopback mode for testing are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit configured to receive a memory write request that is directed to and received by a memory controller. The memory access intercept circuit transmits proxy write data to the memory controller, and intercepts write data directed to the memory controller for the memory write request. The memory access intercept circuit stores the write data in a write data buffer, and, upon intercepting the proxy write data from the memory controller directed to a physical (PHY) interface circuit, retrieves the write data from the write data buffer and transmits the write data to the PHY interface circuit. The memory access intercept circuit subsequently receives, from the PHY interface circuit, loopback data, and stores the loopback data in a read data buffer.

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San Jose, CA, United States of America

Anil Kumar Handenahalli Rajanna