Globalfoundries Inc.

Advanced Micro Devices Corporation

Visa International Service Association

Ati Technologies Ulc

Anil Kumar

Manjunatha Govinda Prabhu

Mahadeva Iyer Natarajan

Jagar Singh

Mahbub Rashed

Sushama Davar

Andy C Wei

Philip Ng

Alain F Loiseau

Shawn Searles

Michael A Nix

Navneet Jain

Moises Emanuel Robinson

Chien-Hsin Lee

Carlin D Cabler

Cathryn Jeanne Christiansen

Srinivas Vadhri

William McMahon

Ronald Gene Filippi, Jr

Suresh Uppal

Tian Shen

Yuncheng Song

Patrick Ryan Justison

Kong Boon Yeap

Luigi Pantisano

Sowmya Saiprasad

Seungman Choi

Premachandran Chirayarikathuveedu

Kelly Alpert

Linjun Cao

Ruchil Kumar Jain

Rakesh Ranjan

An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.

Interrupt cache configuration

A method of controlling transaction velocity limits including: generating a transaction control criterion associated with a parameter; receiving a transaction message associated with a transaction request; analyzing the data associated with the parameter with respect to the transaction control criterion associated with the parameter; automatically generating and communicating at least one of: a processing request message associated with the transaction request if data associated with the at least one parameter in the transaction message does not satisfy the transaction control criterion associated with the at least one parameter, and a rejection response message if data associated with the at least one parameter in the transaction message does satisfy the transaction control criterion associated with the at least one parameter; and generating update data associated with the parameter. A system and computer program product for controlling transaction velocity limits is also disclosed.

Method, system, and computer program product for controlling transaction velocity limits

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

Electrostatic discharge protection device

An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

Parallel test structure

A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.

Calibration devices for I/O driver circuits having switches biased differently for different temperatures

There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

ESD snapback based clamp for finFET

There is set forth herein a semiconductor structure including a plurality of test devices, the plurality of test devices including a first test device and a second test device. A semiconductor structure can also include a waveform generating circuit, the waveform generating circuit configured for application of a first stress signal waveform having a first duty cycle to the first test device, and a second stress signal waveform having a second duty cycle to the second test device. A semiconductor structure can include a selection circuit associated with each of the first test device and the second test device for switching between a stress cycle and a sensing cycle.

Semiconductor structure having test device

An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Planar semiconductor ESD device and method of making same

A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.

Method and apparatus for quantifying defects due to through silicon VIAs in integrated circuits

A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

High voltage protection circuit for non-tolerant integrated circuit

An apparatus including a bias voltage generator and one or more cascode drivers. Each of the one or more cascode drivers may include a plurality of cascode transistors. The bias voltage generator may control the cascode bias voltages provided to the cascode transistors based on a plurality of programmable control bits received by the bias voltage generator. The received plurality of programmable control bits may include a first set of programmable control bits, which may be used to control the magnitude of the cascode bias voltages, and a second set of programmable control bits, which may be used to control the stability of the cascode bias voltages.

Cascode driver with gate oxide protection

Growing community of inventors

Clifton Park, NY, United States of America

Anil Kumar