Altera Corporation

Atmel Corporation

Winbond Electronics Corporation

Magsil Corporation

Windbond Electronics Corp.

Anil Gupta

Srinivas T Reddy

Steven J Schumann

Oron Michael

Krishnakumar Mani

Robin John Jigour

Steve Schumann

Richard G Cliff

Nicola Telecco

Vijay P Adusumilli

Edward S Hui

Kuo-Lung Chen

Kimihiro Satoh

Jannier Maximo Roiz Wilson

Jong Oh Lee

Dae Hyun Kim

A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.

NAND flash memory having an enhanced buffer read capability and method of operation thereof

A NAND flash memory achieves low read latency and avoidance of inadvertent programming and program disturb so that the random access and initial page read speeds of the NAND flash memory are generally comparable to that of a NOR flash memory, while preserving the higher memory density and lower power operation characteristics of traditional NAND flash memory relative to NOR flash memory. The reduction in latency is achieved by a NAND memory array architecture which employs a small NAND string, a dual plane interleaved memory architecture, a partitioned NAND array, selectively coupled local bit lines per each global bit line, and a counter-biasing mechanism to avoid inadvertent programming and program disturb.

NAND flash memory array architecture having low read latency and low program disturb

Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented 'on chip' in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.

On-chip bad block management for NAND flash memory

A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.

Method and apparatus for reading NAND flash memory

A current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor (M) to control driver currents from the current driver circuit, and wherein the transistor (M) has a smaller form factor then otherwise possible by virtue of maintaining a gate thereof at a negative voltage.

Voltage boosting in MRAM current drivers

Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.

MRAM design with local write conductors of reduced cross-sectional area

A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.

Nonvolatile semiconductor memory apparatus

In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately &minus;10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.

Page mode erase in a flash memory array

A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

Look-up table using multi-level decode

In a flash memory array, an internal refresh periodically rewrites the information stored in each of the rows of memory cells in a flash memory. The flash memory array includes a refresh pointer bitline that indicates the row to be refreshed. In a first embodiment of the present invention, the internal refresh is performed automatically after every user erase/program cycle. In second and third embodiments, the user of the of the flash memory array selects when the internal refresh is performed, but the address of the row to be refreshed is supplied internally. In each of the three the embodiments, the internal refresh includes the four operations of SCAN, REFRESH ERASE, REFRESH PROGRAM, and INCREMENT.

Flash memory array with internal refresh

In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately -10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.

A flash memory array architecture comprising a flash memory array, first and second memory buffer, and I/O interface circuit which has several operating modes which permit data to be read from the flash memory array, several operating modes which permit data to be programmed into the flash memory array, and a mode for rewriting the data in the flash memory array. In the four read modes, one of the pages stored in the flash memory array is read, the data stored in either of first or second memory buffers is read, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers, the data in one of the pages of data stored in the flash memory array is read and then compared to the data read from either of first or second memory buffers. In the four write modes, data from an input stream is written into a selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array, data in either of first or second memory buffers is written into a previously erased page in the flash memory array, and data from an input stream is written into the selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array. In the auto page rewrite mode, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers. The data stored in the page of the flash memory array just read is erased, and then in the same cycle, the page of data stored in the selected first or second memory buffer is written into the erased page in the flash memory array.

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San Jose, CA, United States of America

Anil Gupta