Motorola Corporation

Anil Gercekci

Heinz Bernhard Maeder

Michel Bron

Roland H Schwarz

Eric Boulian

Alain Duret

Peter D Hudson

A data storage device (9) comprises an array of electronic memory locations (20) for storing data. An address input terminal (10) provides coupling to an address source and is coupled to provide first address signals from the address source to address the memory locations of the array (20). A data output terminal (12) provides coupling to a data reception arrangement and is connected to the array (20) for receiving data signals therefrom in response to the address signals. The data signals are indicative of the data stored in the memory locations addressed by the address signals. An address encryption arrangement (14) is coupled between the address input terminal (10) and the array (20) for encrypting the first address signals. The address encryption arrangement (14) contains encrypting data which is protected from direct optical determination, the encrypting data being used to encrypt the first address signals.

Data storage device

A bus system has a main bus and an internal bus. The main bus is coupled to a number of driver units which drive data onto the main bus and to receiver units which respond to that data and provide response data to the main bus. A logic unit provides two-way communication directly between the main and internal buses and allows testing of individual driver and receiver units independently of other units.

Bus system having a system bus, an internal bus with functional units

A clock signal conditioning circuit (100) for use in a smart card (102) has an input node (112) for receiving an applied clock signal, an output node (126) for producing a conditioned clock signal, a rising/falling edge detector (118) for detecting edges in the received clock signal, a bistable device (122) for forming at the output node a clock signal in response to the edge detector, and a timer (120, 124) for inhibiting switching of the bistable device for a predetermined time (T) following detection by the edge detector of an edge. Such a clock signal conditioning circuit provides a conditioned clock signal which is substantially independent of variations in the duty cycle of the applied clock signal and is substantially immune to glitches in the applied clock signal.

Clock signal conditioning circuit

A debit card of the type having an integrated circuit on a semiconductor chip embedded in a plastic card includes logic circuitry (10), a counter (2), a ROM (6) and an EEPROM (8) for storing the value of the counter between transactions. By providing two EEPROMs (8A, 8B) in parallel whose values are compared by a comparator (24), the security of the card is increased since operation of the card may be blocked if the two values are not the same, indicating that attempts have been made to fraudulently reprogram the card.

Memory cards

An integrated circuit for a data or 'smart' card includes a non-volatile memory (8) having a transport code preprogrammed therein, control circuitry (10), a comparator (24) for comprising an externally-applied code and the transport code, and a fuse (26) which is blown if the two codes match thereby allowing the card to be initialised with a personal identification number and initial credit values. A second fuse (28) may also be provided which is blown if the two codes do not match and sensing means (32, 34) sense the status of the two fuses (26, 28) and block any further attempts to initialise the card if the second fuse (28) is blown and the first fuse (26) is not.

Data card circuits

A data processor (2) including a watchdog timer (8) comprising: a first memory (4) holding a primary operating routine for cyclic execution during operation of the data processor, an address bus (6) for addressing locations in said first memory means, a timer (10) for continuous operation during operation of the data processor and for effecting a system reset in response to the timer reaching a predetermined value, the primary operating routine including at at least one predetermined location an instruction to reset the timer, whereby in normal operation of the data processor the timer does not reach the predetermined value, wherein the data processor further includes a second memory (12) for holding the address of the location containing the instruction to reset the timer, and a comparator (16) coupled to the address bus and the timer for preventing the timer from being reset in response to an instruction to reset the timer unless the address on the address bus is held in the second memory.

Watchdog timer

An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.

Means and method for disabling access to a memory

A programmable transistor is provided adjacent to a programmable read only memory. A latch is used in conjunction with the programmable transistor and data is written into the latch. If the programmable transistor is programmed the output of the latch will be modified, however, if the programmable transistor is not programmed the output of the latch will not be modified when it is read. The programming pads used to program the programmable transistor are severed so they are no longer functional once the programmable transistor has been programmed. Therefore if someone erases the programmable read only meory the programmable transistor is also erased and cannot be reprogrammed.

Prom erase detector

A method of automatically searching for an RF carrier uses a synthesized frequency. The synthesized frequency is generated by a voltage controlled oscillator which is part of a phase locked loop. The phase locked loop has a programmable divider which is controlled by a phase locked loop controller. The phase locked loop controller receives inputs from a frequency discriminator which is a portion of an RF receiver which is receiving the RF signals. The search is accomplished by using a frequency sweep rather than searching for a carrier at allocated frequency positions. When the search is initiated, large frequency steps are taken until a carrier signal is passed up and then the steps are decreased in size and inversed until the carrier signal is encountered again.

Method for automatically searching for an RF station

An oscillator for generating oscillation signals. The oscillation signals are initiated in response to an applied start signal and begin at a fixed predetermined phase. Hence, the oscillator is suitable for use in phase dependent timing systems to inhibit phase jitter which could otherwise occur. The oscillator includes an inverting amplifier and phase shifting feedback network for establishing and maintaining oscillations. The phase shifting feedback network includes a series coupled coil between the output and input of the inverting amplifier. A bias circuit is included for injecting direct current through the coil when oscillation is inhibited to generate a direct current magnetic field in the coil. The magnetic field ensures that, in response to the start signal, the oscillation signals begin at said fixed phase.

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Geneva, Switzerland

Anil Gercekci